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公开(公告)号：US07091743B2
公开(公告)日：2006-08-15
申请号：US10680756
申请日：2003-10-07
申请人： Michael J. Boudreaux , Adam J. Courchesne , Jason M. Norman , Mark S. Styduhar , Sebastian T. Ventrone
发明人： Michael J. Boudreaux , Adam J. Courchesne , Jason M. Norman , Mark S. Styduhar , Sebastian T. Ventrone
IPC分类号： H03K17/16
CPC分类号： G06F13/4269
摘要： A structure and associated method to control a flow of data on a semiconductor device. A transmitter, receiver and transmission line are formed within the semiconductor device. The transmitter, receiver, and transmission line are adapted to control data transfer between a first core and a second core within the semiconductor device. The transmitter is adapted to send a signal over the transmission line to the receiver adapted to receive the signal. The receiver is further adapted to create an impedance mismatch to indicate that the second core is unable to transfer the data. The transmitter is adapted to detect the impedance mismatch.
摘要翻译： 一种用于控制半导体器件上的数据流的结构和相关方法。 在半导体器件内形成发射器，接收器和传输线。 发射器，接收器和传输线适于控制半导体器件内的第一芯和第二芯之间的数据传输。 发射机适于通过传输线路将信号发送到适于接收信号的接收机。 接收机还适于产生阻抗失配以指示第二核心不能传送数据。 发射机适用于检测阻抗失配。
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公开(公告)号：US07139881B2
公开(公告)日：2006-11-21
申请号：US10605366
申请日：2003-09-25
CPC分类号： G06F12/0284
摘要： A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other said local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.
摘要翻译： 一种半导体器件上传输数据的结构和相关方法，包括：半导体器件内的多个系统。 每个系统包括至少一个处理设备和本地存储器结构。 每个处理设备电耦合到每个系统内的每个本地存储器结构。 每个本地存储器结构电耦合到每个其他所述本地存储器结构。 每个本地存储器结构适于与每个处理设备共享地址空间。 每个处理设备适于将数据和指令传送到每个本地存储器结构。
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3.发明授权Critical path redundant logic for mitigation of hardware across chip variation 有权用于缓解跨芯片变化的硬件的关键路径冗余逻辑公开(公告)号：US07898286B2
公开(公告)日：2011-03-01
申请号：US12369066
申请日：2009-02-11
申请人： Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
IPC分类号： H03K19/00
CPC分类号： G01R31/31725
摘要： Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.
摘要翻译： 用于管芯或芯片的跨管芯连接结构和方法包括具有缓冲器驱动器和旁路的缓冲器元件以及耦合到缓冲器元件的控制线，以便为每个相应的缓冲元件选择缓冲器驱动器和旁路中的一个。 逻辑网络被布置成具有缓冲元件以形成功能路径，测试单元被构造和布置以测试功能路径并耦合到控制线，以及配置存储寄存器，用于设置所选缓冲器驱动器和 绕过每个通过的功能路径。
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4.发明申请Transition Balancing For Noise Reduction/Di/Dt Reduction During Design, Synthesis, and Physical Design 有权在设计，综合和物理设计过程中减少平衡降噪/减少Di / Dt公开(公告)号：US20090106724A1
公开(公告)日：2009-04-23
申请号：US11875032
申请日：2007-10-19
申请人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068
摘要： An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.
摘要翻译： 示出了用于降噪的设计结构的实施例，其包括合成顺序锁存器的块，例如流水线电路架构或时钟域，其包括组合逻辑，合成根或主时钟和至少一个相移子域 每个块的时钟，将主输入和主输出分配给根时钟，将该块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相位时钟输入， 移位子域时钟输入，为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。
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公开(公告)号：US20080046772A1
公开(公告)日：2008-02-21
申请号：US11457916
申请日：2006-07-17
IPC分类号： G06F1/00
CPC分类号： G06F1/10
摘要： A method and system for reducing clock noises are disclosed. A clock signal includes active edges and inactive edges. Inactive edges produce clock noise but are not critical to the functionality of the clock signal. That is, only active edges are critical to proper timing of an integrated circuit (IC). As such, inactive edges of clock signals to clocked elements of an IC may be shifted to be misaligned to one another. As a consequence, peak noise produced by the inactive edges will be spread over a large area and therefore will be reduced in amplitude.
摘要翻译： 公开了一种减少时钟噪声的方法和系统。 时钟信号包括有效边沿和非活动边沿。 无效边沿产生时钟噪声，但并不对时钟信号的功能至关重要。 也就是说，只有有效边沿对于集成电路（IC）的正确定时至关重要。 因此，到IC的时钟元件的时钟信号的无效边沿可能被移位以彼此不对准。 结果，由无源边缘产生的峰值噪声将在大面积上扩展，因此幅度将被减小。
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公开(公告)号：US07286770B2
公开(公告)日：2007-10-23
申请号：US10604410
申请日：2003-07-18
申请人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
发明人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
IPC分类号： H04B10/00
CPC分类号： G02B6/43
摘要： Disclosed is an integrated circuit comprising a plurality of cores attached to at least one transmitter and receiver, an optical transmission network embedded within the wire levels of the integrated circuit, and wherein the transmitter and receivers send and receive data on the network. Also disclosed is a method of transmitting signals within an integrated circuit comprising an integrated circuit comprising a plurality of cores and optical paths, selecting an optical path from the plurality of optical paths for transmitting data, and transmitting the data on the selected optical path. Also disclosed is an integrated circuit comprising an optical transmission network, a plurality of cores, and a plurality of controllers, all three being operatively attached to each other.
摘要翻译： 公开了一种集成电路，其包括附接到至少一个发射机和接收机的多个核心，嵌入在集成电路的有线电平内的光传输网络，并且其中发射机和接收机在网络上发送和接收数据。 还公开了一种在包括多个核心和光路的集成电路的集成电路内传输信号的方法，从多个光路中选择用于发送数据的光路，以及在所选择的光路上发送数据。 还公开了一种集成电路，其包括光传输网络，多个核心和多个控制器，所有三个可操作地彼此连接。
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7.发明授权Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design 失效在设计，合成和物理设计过程中，降噪/减少/减少Di / Dt的转换平衡公开(公告)号：US07643591B2
公开(公告)日：2010-01-05
申请号：US11460065
申请日：2006-07-26
申请人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
IPC分类号： H04L7/00
CPC分类号： H04L7/02
摘要： A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.
摘要翻译： 一种用于噪声的方法，包括合成诸如流水线电路架构或时钟域的顺序锁存器的块，其包括组合逻辑，合成根或主时钟以及用于每个块的至少一个相移子域时钟， 输入和主输出到根时钟，将块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相移子域时钟输入， 为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。
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公开(公告)号：US20080212977A1
公开(公告)日：2008-09-04
申请号：US11772378
申请日：2007-07-02
申请人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
发明人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
IPC分类号： H04B10/00
CPC分类号： G02B6/43
摘要： An optical transmission method. Signal transmissions between cores of an integrated circuit are performed. Each signal transmission is between two cores of a different pair of cores of the integrated circuit. Each signal transmission includes transmission of an optical signal in the visible or infrared portion of the electromagnetic spectrum at a wavelength that is specific to each different pair of cores and is a different wavelength for each different pair of cores. There is no overhead for decoding or arbitration in preforming the signal transmissions that would otherwise exist if a same wavelength for the optical signals were permitted for pairs of cores of the different pairs of cores.
摘要翻译： 光传输方法。 执行集成电路的核心之间的信号传输。 每个信号传输在集成电路的不同核心的两个核之间。 每个信号传输包括以对于每个不同的核对特定的波长的电磁光谱的可见光或红外部分中的光信号的传输，并且对于每个不同的一对核心是不同的波长。 如果对于不同核心对的核对允许相同的光信号波长，则在进行信号传输时，没有解码或仲裁的开销。
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9.发明申请TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DESIGN, SYNTHESIS, AND PHYSICAL DESIGN 失效在设计，合成和物理设计期间减少噪声的转换平衡/ di / dt减少公开(公告)号：US20080043890A1
公开(公告)日：2008-02-21
申请号：US11460065
申请日：2006-07-26
申请人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
IPC分类号： H04L7/00
CPC分类号： H04L7/02
摘要： A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.
摘要翻译： 一种用于噪声的方法，包括合成诸如流水线电路架构或时钟域的顺序锁存器的块，其包括组合逻辑，合成根或主时钟以及用于每个块的至少一个相移子域时钟， 输入和主输出到根时钟，将块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相移子域时钟输入， 为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。
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公开(公告)号：US07743270B2
公开(公告)日：2010-06-22
申请号：US11530544
申请日：2006-09-11
CPC分类号： G06F1/04 , G06F1/10 , G06F17/5031 , G06F17/505 , G06F2217/62
摘要： A method, system and computer program product reducing clock noise generated by clock signals in an integrated circuit (IC) are disclosed. Conventional IC design attempts to ensure coincident clock active edge arrival times for all clocked elements. The coincident active clock edges generate coincident noise currents, which elevates the total noise current. The current invention assigns clock arrival times for clocked elements of an IC based on a desired clock arrival time distribution such that active clock edges are not coincident. As a consequence, the total noise would be spread over a large portion of the clock cycle, thus reducing the noise magnitude substantially.
摘要翻译： 公开了减少由集成电路（IC）中的时钟信号产生的时钟噪声的方法，系统和计算机程序产品。 传统IC设计尝试确保所有时钟元件的重合时钟主动边沿到达时间。 重合的有效时钟边沿产生一致的噪声电流，这提高了总的噪声电流。 本发明基于期望的时钟到达时间分布来为IC的时钟元件分配时钟到达时间，使得活动时钟边缘不一致。 因此，总噪声将在时钟周期的大部分时间内扩展，从而大大降低噪声幅度。
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