公开(公告)号：US06467160B1

公开(公告)日：2002-10-22

申请号：US09537960

申请日：2000-03-28

申请人： Michael J. Cummings ,  Michael V. Longo ,  Curtis L. Miller ,  Thomas R. Miller ,  Michael Wozniak

发明人： Michael J. Cummings ,  Michael V. Longo ,  Curtis L. Miller ,  Thomas R. Miller ,  Michael Wozniak

IPC分类号： H01K310

CPC分类号： H05K3/427 ,  H05K3/0094 ,  H05K3/064 ,  H05K2201/0959 ,  H05K2203/1394 ,  Y10T29/49128 ,  Y10T29/49165

摘要： A method of making a circuitized substrate having plated through holes free of filler material is provided. The method includes the steps of providing a dielectric substrate having first and second opposite faces. At least one via hole is formed from one face to the other. A first electrically conductive layer is applied onto the top and bottom faces of the dielectric member and onto the side wall of the via. First layers of photoresist are applied to each layer of conductive material and entering at least partially into the via hole. The first layers of photoresist are selectively exposed and developed to remove all of the photoresist, except that photoresist which is disposed in the via holes. Thereafter, a portion of the faces of the metal coatings on the surfaces of dielectric material and any photoresist remaining in the holes extending above the layers of electrically conductive material are removed to form a planar surface thinner than the thickness of the metal in the through hole. Thereafter, a second layer of photoresist material is applied to both the surfaces of the metal on both faces of the dielectric material and exposed to a desired circuit pattern. Thereafter, the second layers of the photoresist material are developed to reveal the underlying metal which is then etched to form a circuit pattern in the metal layer on both faces. Thereafter, the second layers of the remaining photoresist are stripped and also the photoresist remaining in the hole is stripped, thereby to provide a circuitized substrate with plated through holes having an opening extending from the upper face of the substrate to the lower face of the substrate.

摘要翻译： 提供了一种制造电路化基板的方法，该基板具有不含填料的电镀通孔。 该方法包括提供具有第一和第二相对面的电介质基板的步骤。 至少一个通孔从一个面到另一个形成。 将第一导电层施加到电介质构件的顶表面和底表面上并通过通孔的侧壁。 将第一层光致抗蚀剂施加到每个导电材料层并且至少部分地进入通孔。 除了设置在通孔中的光致抗蚀剂之外，第一层光致抗蚀剂被选择性地曝光和显影以除去所有光致抗蚀剂。 此后，介电材料表面上的金属涂层表面的一部分和残留在延伸到导电材料层之上的孔中的任何光致抗蚀剂被去除以形成比通孔中的金属厚度更薄的平面 。 此后，将第二层光致抗蚀剂材料施加到电介质材料的两个表面上的金属的两个表面上并暴露于期望的电路图案。 此后，第二层光致抗蚀剂材料被显影以露出下面的金属，然后将其蚀刻以在两面上的金属层中形成电路图案。 此后，残留的光致抗蚀剂的第二层被剥离，并且剥离残留在孔中的光致抗蚀剂，从而为电路化基板提供具有从基板的上表面延伸到基板的下表面的开口的电镀通孔 。

公开(公告)号：US06429390B1

公开(公告)日：2002-08-06

申请号：US09804535

申请日：2001-03-12

申请人： Michael J. Cummings ,  Robert J. Lerner ,  Michael V. Longo ,  Andrew M. Seman ,  Raymond C. Tompkins ,  Timothy L. Wells

发明人： Michael J. Cummings ,  Robert J. Lerner ,  Michael V. Longo ,  Andrew M. Seman ,  Raymond C. Tompkins ,  Timothy L. Wells

IPC分类号： H01R1204

CPC分类号： H05K1/114 ,  H05K1/0269 ,  H05K1/111 ,  H05K2201/09381 ,  H05K2201/09745 ,  H05K2201/10734

摘要： A wiring board for mounting an electrical device, which has an array of connectors thereon arranged in a grid pattern, wherein the connectors have at least two levels of criticality of connection to the substrate. The substrate has a plurality of mounting structure or features arranged in the same grid pattern to connect with the array of connectors on the electrical device. The mounting structures or features are divided into a plurality of at least two groups, with each group corresponding to a level of criticality of the connectors on the device. Each group of mounting structures has a discernible feature differing from each other group, to thereby permit different levels of inspection criteria for each group. The invention also contemplates a method of forming a substrate having the features for connecting the connectors on the device that have different levels of criticality

摘要翻译： 一种用于安装电气装置的布线板，其具有以栅格图案布置的连接器阵列，其中所述连接器具有至少两个级别的与所述基板的连接关键性。 衬底具有以相同格栅图案布置的多个安装结构或特征，以与电气设备上的连接器阵列连接。 安装结构或特征被分成多个至少两个组，每个组对应于装置上连接器的关键性水平。 每组安装结构具有彼此不同的可辨别特征，从而允许每组的不同级别的检查标准。 本发明还考虑了一种形成具有用于连接具有不同等级临界度的装置上的连接器的特征的基板的方法

公开(公告)号：US06887651B2

公开(公告)日：2005-05-03

申请号：US10304143

申请日：2002-11-25

申请人： Ashwinkumar C. Bhatt ,  Brant S. Blomberg ,  Ross W. Keesler ,  Michael V. Longo ,  Eboney J. N. Smith

发明人： Ashwinkumar C. Bhatt ,  Brant S. Blomberg ,  Ross W. Keesler ,  Michael V. Longo ,  Eboney J. N. Smith

IPC分类号： G03F7/00 ,  G03F7/16 ,  H05K3/00 ,  H05K3/06 ,  G03F7/26

CPC分类号： H05K3/064 ,  G03F7/0035 ,  G03F7/164 ,  H05K3/0094 ,  H05K2203/0577 ,  H05K2203/135 ,  H05K2203/1394

摘要： A hybrid photolithography process for printed circuit board patterning combines two types of photoresist applications to achieve superior protection of printed circuit board (PCB) ‘plated through holes’ (PTH). In a first step, electro-deposited (ED) photoresist (also known as “ED resist”) is applied to a fully copper plated PCB including the ‘plated through holes’ to protect the outer layers and the ‘plated through holes’ from copper etchant solution. In a second step, the electro-deposited photoresist is imaged (exposed) and patterned (developed). In a third step, after developing the circuit image, a layer of Dry Film resist is applied to the panel of the PCB on top of the developed electro-deposited (ED) photoresist. This Dry Film resist layer will ‘tent’ the plated through holes by adding an extra layer of protection to the plated through holes. In a fourth step, the dry film resist is then exposed and developed. At this point, the PCB is etched as normal and all subsequent processing remains unchanged.

摘要翻译： 用于印刷电路板图案的混合光刻工艺组合了两种类型的光致抗蚀剂应用，以实现印刷电路板（PCB）“电镀通孔”（PTH）的优异保护。 在第一步中，将电沉积（ED）光致抗蚀剂（也称为“ED抗蚀剂”）施加到包括“电镀通孔”的完全镀铜的PCB上，以保护外层和“电镀通孔”与铜 蚀刻液 在第二步中，将电沉积的光致抗蚀剂成像（曝光）并图案化（显影）。 在第三步骤中，在显影电路图像之后，将一层干膜抗蚀剂施加到显影的电沉积（ED）光致抗蚀剂顶部的PCB板上。 该干膜抗蚀剂层将通过向电镀通孔添加额外的保护层来“掩盖”电镀通孔。 在第四步骤中，然后将干膜抗蚀剂曝光和显影。 此时，PCB正常蚀刻，所有后续处理保持不变。