公开(公告)号：US4534044A

公开(公告)日：1985-08-06

申请号：US490613

申请日：1983-05-02

Applicant: Michael J. Funke ,  Douglas A. Topliffe ,  Donald J. Rathbun

Inventor： Michael J. Funke ,  Douglas A. Topliffe ,  Donald J. Rathbun

IPC: G11B20/14 ,  H03L7/089 ,  H03L7/183 ,  H03L7/06 ,  G11B5/09

CPC classification number: H03L7/0891 ,  G11B20/1419 ,  G11B20/1423 ,  H03L7/183

Abstract: A diskette read data recovery system generates a clock which is locked to an incoming data stream. In a phase locked loop, a signal generated by an oscillator and frequency dividers is compared in phase to the incoming data stream to provide first or second signals depending on whether the incoming data signal leads or lags the clock signal. In order that the system may handle different types of incoming signals, different frequency divider circuits in the phase locked loop are selected for different incoming signals.

Abstract translation: 磁盘读取数据恢复系统生成锁定到输入数据流的时钟。 在锁相环中，由振荡器和分频器产生的信号与输入数据流进行相位比较，以根据输入的数据信号是导通还是滞后于时钟信号来提供第一或第二信号。 为了使系统可以处理不同类型的输入信号，针对不同的输入信号选择锁相环中的不同分频器电路。

公开(公告)号：US4161778A

公开(公告)日：1979-07-17

申请号：US816985

申请日：1977-07-19

Applicant: Edward F. Getson, Jr. ,  John H. Kelley ,  Donald J. Rathbun ,  Albert T. McLaughlin

Inventor： Edward F. Getson, Jr. ,  John H. Kelley ,  Donald J. Rathbun ,  Albert T. McLaughlin

IPC: G06F3/06 ,  G06F13/36

CPC classification number: G06F13/36

Abstract: In a data processing system wherein a plurality of functional units are interconnected by way of a common communication bus in an environment of high data transfer rates, a logic control system is provided for interjecting firmware control during a data transfer between a disk device and main memory to accommodate unsolicited bus requests without incurring data errors or compromising the data transfer rate. Data transferred between the disk device and a disk controller interfacing directly with the common bus is routed through a FIFO (first-in-first-out) buffer under hardware control. The buffer signals the absence of data in its input register and the presence of data in its output register. The signals are logically combined and ANDed with a firmware controlled logic gate to indicate the occurrence of data transfer states. During such transfer states, data is transferred under hardware control between the FIFO buffer and main memory. When the input register of the FIFO buffer is filled during a data transfer from main memory to the disk device, or when the FIFO buffer is empty during a transfer of data from the disk device to main memory, hardware controlled data transfers are not required. In that event the firmware control system is permitted to access the common bus to service unsolicited bus requests.

Abstract translation: 在数据处理系统中，其中多个功能单元通过公共通信总线在高数据传输速率的环境中互连，提供逻辑控制系统，用于在盘设备和主存储器之间的数据传输期间插入固件控制 以容纳未经请求的总线请求，而不会导致数据错误或损害数据传输速率。 磁盘设备与直接与公共总线接口的磁盘控制器之间传输的数据通过硬件控制下的FIFO（先进先出）缓冲器进行路由。 缓冲区表示其输入寄存器中不存在数据，并在其输出寄存器中显示数据。 信号被逻辑地组合并与固件控制的逻辑门进行“与”，以指示数据传送状态的发生。 在这种传输状态期间，在FIFO缓冲器和主存储器之间的硬件控制下传送数据。 在从主存储器到磁盘设备的数据传输期间填充FIFO缓冲器的输入寄存器时，或者在将数据从磁盘设备传送到主存储器期间FIFO缓冲器为空时，不需要硬件控制的数据传输。 在这种情况下，固件控制系统被允许访问公共总线来服务主动请求。

公开(公告)号：US5155810A

公开(公告)日：1992-10-13

申请号：US295683

申请日：1989-01-10

Applicant: John L. McNamara, Jr. ,  Donald J. Rathbun

Inventor： John L. McNamara, Jr. ,  Donald J. Rathbun

IPC: G06F13/12

CPC classification number: G06F13/122

Abstract: An adapter is connected between a peripheral controller and an intelligent peripheral device. The adapter allows the peripheral device to communicate with the controller. The adapter has control logic rather than a microprocessor for transmitting and receiving data. The control logic is comprised of combinatorial logic circuitry and a command register. The command register allows the controller to configure the cominatorial logic circuitry in order to control adapter operation.

Abstract translation: 外部控制器和智能外围设备之间连接有一个适配器。 适配器允许外围设备与控制器通信。 适配器具有控制逻辑，而不是用于发送和接收数据的微处理器。 控制逻辑由组合逻辑电路和命令寄存器组成。 命令寄存器允许控制器配置组合逻辑电路，以控制适配器的操作。

公开(公告)号：US4173027A

公开(公告)日：1979-10-30

申请号：US862258

申请日：1977-12-20

Applicant: Donald J. Rathbun

Inventor： Donald J. Rathbun

IPC: G11B20/10 ,  G11B20/14 ,  G11B27/10 ,  G11B5/09

CPC classification number: G11B20/10212 ,  G11B20/1423 ,  G11B27/102

Abstract: A logic system is provided for precompensating data and clock bits of a formatted binary information stream during a modified frequency modulation (MFM) encoding for recording on a magnetic medium. The binary information stream is formatted into a gap field, an address preamble field, an address mark field and a data field. Clock bit generation is inhibited during the gap and address preamble fields. Further, a second of three clock bits occurring during the high order half-byte of the address mark field is suppressed to provide a modified MFM (M.sup.2 FM) field. An address mark is provided thereby for indicating the near proximity of a data field. Beginning with the low order half-byte of the address mark field, both MFM clock precompensation and MFM data precompensation is applied as required. The amount of peak shift occurring in the MFM encoded information stream after precompensation is substantially reduced.

Abstract translation: 提供了一种逻辑系统，用于在用于在磁介质上记录的修改的频率调制（MFM）编码期间对格式化的二进制信息流的数据和时钟位进行预补偿。 二进制信息流被格式化为间隙字段，地址前导字段，地址标记字段和数据字段。 在间隙和地址前同步码字段期间抑制时钟位产生。 此外，抑制了在地址标记字段的高位半字节期间发生的三个时钟位中的第二个，以提供修改的MFM（M2FM）字段。 由此提供地址标记，用于指示数据字段的接近度。 从地址标记字段的低位半字节开始，根据需要应用MFM时钟预补偿和MFM数据预补偿。 在预补偿之后，MFM编码信息流中发生的峰值偏移量大大降低。

公开(公告)号：US4159532A

公开(公告)日：1979-06-26

申请号：US821931

申请日：1977-08-04

Applicant: Edward F. Getson, Jr. ,  John H. Kelley ,  Albert T. McLaughlin ,  Donald J. Rathbun

Inventor： Edward F. Getson, Jr. ,  John H. Kelley ,  Albert T. McLaughlin ,  Donald J. Rathbun

IPC: G06F7/00 ,  G06F5/10 ,  G06F5/14 ,  G06F13/12 ,  G06F13/28 ,  G06F13/38 ,  G06F13/00

CPC classification number: G06F5/14 ,  G06F13/124 ,  G06F13/28

Abstract: A logic data control system including a first-in-first-out (FIFO) buffer predictor is provided for the transfer of data between a main memory unit and a peripheral control unit of a data processing system. Data from main memory is stored into the input registers of the peripheral unit, and thereafter loaded into an array of data FIFOs for transfer to a peripheral storage device. A predictor FIFO operates in parallel with the data FIFOs, and is loaded with a dummy or flag byte each time a data request is made to main memory. When a data word is loaded into the data FIFOs, the input register of the predictor FIFO is sensed. If the flag byte in the predictor FIFO has dropped from the input register into the FIFO stack, a request is issued to main memory for an additional data word. When the data FIFOs are filled, the predictor FIFO also is filled and cannot generate an additional data request until a data byte has been unloaded from the data FIFOs to a peripheral storage device. The input register to the predictor FIFO thereupon is emptied, and another data request may be made to main memory.

Abstract translation: 提供了包括先进先出（FIFO）缓冲器预测器的逻辑数据控制系统，用于在数据处理系统的主存储器单元和外围控制单元之间传送数据。 来自主存储器的数据被存储到外围单元的输入寄存器中，然后被加载到用于传送到外围存储设备的数据FIFO阵列中。 预测器FIFO与数据FIFO并行操作，并且每当向主存储器发出数据请求时，都加载虚拟或标志字节。 当数据字被加载到数据FIFO中时，检测预测器FIFO的输入寄存器。 如果预测器FIFO中的标志字节从输入寄存器下降到FIFO堆栈，则向主存储器发出附加数据字的请求。 当数据FIFO被填充时，预测器FIFO也被填充，并且在数据字节从数据FIFO被卸载到外围存储设备之前不能产生附加的数据请求。 到其中的预测器FIFO的输入寄存器被清空，并且可以对主存储器进行另一数据请求。

公开(公告)号：US5206948A

公开(公告)日：1993-04-27

申请号：US455666

申请日：1989-12-22

Applicant: Douglas J. De Angelis ,  Henry W. J. Maddox ,  Arthur Peters ,  Donald J. Rathbun ,  William L. Saltmarsh

Inventor： Douglas J. De Angelis ,  Henry W. J. Maddox ,  Arthur Peters ,  Donald J. Rathbun ,  William L. Saltmarsh

IPC: G06F11/34

CPC classification number: G06F11/348 ,  G06F11/3466 ,  G06F11/349 ,  G06F11/3495

Abstract: A monitoring means for selectively detecting and recording signals representing at selected points within a system, includes trigger generation logic responsive to selected bus signals for generating trigger signals representing the occurrence of selected conditions, and a recording memory for recording the conditions thereupon, a trigger selection logic for selecting trigger outputs corresponding to the trigger signals. The trigger selection logic includes a trigger enabling memory for storing selectable trigger enabling codes, wherein each enabling code corresponds to a trigger signal, and trigger output logic responsive to the trigger enabling codes and to the trigger signals for providing trigger outputs. The trigger enabling codes include bus enabling codes representing selected conditions on a bus of the system, trigger sequence enabling codes corresponding to sequential combinations of trigger signals and external trigger enabling codes corresponding to triggers external to the system. The enabling codes may select trigger signals to be used in logical AND or OR functions in generating a trigger output or in substitution for a bus trigger signal.

Abstract translation: 用于选择性地检测和记录表示在系统内的选定点处的信号的监视装置包括响应于所选择的总线信号的触发生成逻辑，用于产生表示所选条件出现的触发信号，以及用于记录其上的条件的记录存储器，触发选择 用于选择与触发信号对应的触发输出的逻辑。 触发选择逻辑包括触发器，用于存储可选择的触发使能代码，其中每个使能代码对应于触发信号，并且响应于触发使能代码和触发信号触发输出逻辑以提供触发输出。 触发使能代码包括表示系统总线上的选定条件的总线使能代码，触发序列使能对应于触发信号的顺序组合的代码和对应于系统外部的触发的外部触发使能代码。 启用代码可以选择在逻辑“或”或“或”功能中使用的触发信号来产生触发输出或代替总线触发信号。

公开(公告)号：US4212038A

公开(公告)日：1980-07-08

申请号：US866441

申请日：1978-01-03

Applicant: Donald J. Rathbun

Inventor： Donald J. Rathbun

IPC: H03M5/12 ,  G11B20/14 ,  H03M5/14 ,  H04L25/49 ,  H03K13/24 ,  G11B5/09

CPC classification number: G11B20/1423

Abstract: A logic system requiring no tuning adjustments is provided for converting an MFM encoded information stream read from a mass storage medium to a non-return-to-zero (NRZ) information stream. The MFM encoded information stream is routed through an input shift register to provide plural information bit cells in parallel. Outputs of the shift register are sampled with a multiplexer to generate timing strobes for detecting an address mark, and for identifying clock bits, data bits and logic zero data appearing in the MFM encoded data field following the address mark. Clock bits are separated from the data, and both data bits and logic zero data are applied serially to an output shift register to form a serial NRZ data stream. Each time a data bit or logic zero data is loaded into the output shift register, a synchronization strobe is generated to transfer the NRZ data to succeeding systems.

Abstract translation: 提供了不需要调谐调整的逻辑系统，用于将从大容量存储介质读取的MFM编码信息流转换为非归零（NRZ）信息流。 MFM编码信息流通过输入移位寄存器进行路由以并行提供多个信息位单元。 移位寄存器的输出用多路复用器进行采样，以产生用于检测地址标记的定时选通信号，并用于识别出现在地址标记之后的MFM编码数据字段中的时钟位，数据位和逻辑零数据。 时钟位与数据分离，数据位和逻辑零数据串行地应用于输出移位寄存器以形成串行NRZ数据流。 每当将数据位或逻辑零数据加载到输出移位寄存器中时，产生同步选通脉冲以将NRZ数据传送到后续系统。

公开(公告)号：US4034348A

公开(公告)日：1977-07-05

申请号：US700276

申请日：1976-06-28

Applicant: Donald J. Rathbun

Inventor： Donald J. Rathbun

IPC: H03M5/12 ,  G11B20/14 ,  H04L25/49 ,  G06F7/28 ,  H03K5/00

CPC classification number: G11B20/1419

Abstract: Data and clock bits are sampled by use of two delay means such as shift registers which are enabled at a clock rate which is set so that a first such delay means coupled to receive the bits includes no more than one bit therein at any time. The receipt of a bit substantially at the midway point of the second delay means, which is coupled serially to receive bits from the first delay means, causes a sampling signal to be generated in response to which a determination is made as to whether another bit has been received by the first delay means. Further logic is provided to recover the data bits.

Abstract translation: 通过使用诸如移位寄存器的两个延迟装置对数据和时钟位进行采样，时钟速率被设置为使得耦合到接收位的第一这样的延迟装置在任何时间都不超过一位。 基本上在第二延迟装置的中点处接收一个位，其被串行耦合以从第一延迟装置接收位，导致产生采样信号，响应于此，确定另一位是否具有 被第一个延迟手段所接收。 提供进一步的逻辑来恢复数据位。

公开(公告)号：US5226153A

公开(公告)日：1993-07-06

申请号：US944793

申请日：1992-09-14

Applicant: Douglas J. DeAngelis ,  Henry W. J. Maddox ,  Arthur Peters ,  Donald J. Rathbun

Inventor： Douglas J. DeAngelis ,  Henry W. J. Maddox ,  Arthur Peters ,  Donald J. Rathbun

IPC: G06F11/34

CPC classification number: G06F11/3466 ,  G06F11/348 ,  G06F11/349 ,  G06F11/3495

Abstract: A monitor for selectively detecting and recording conditions at selected points within a system during operation includes trigger logic connected from first selected points and responsive to selected conditions occurring at each of the first points for generating corresponding trigger outputs representing the occurrence of the selected conditions and a silo bank memory having a sub-silo for each second point. Each sub-silo has a first sub-silo segment with data inputs connected from the corresponding second point for recording data from the second point and a second sub-silo segment with data inputs connected from a time stamp generator. Silo write control logic is responsive to the trigger outputs to write the data representing the conditions present at each second point and the time stamp output of the time stamp generator into the corresponding sub-silo segments of the silo bank upon occurrence of a corresponding trigger output so that each condition recorded in the silo bank memory as the result of a trigger output has associated with it the time stamp count representing the relative time of occurrence of the trigger output.

Abstract translation: 用于在操作期间选择性地检测和记录系统内的选定点处的条件的监视器包括从第一选择点连接的触发逻辑，并且响应于在每个第一点处出现的选定条件，以产生表示选定条件的出现的相应触发输出，以及 筒仓组存储器具有用于每个第二点的子仓库。 每个子仓具有第一子仓段，其中数据输入从相应的第二点连接，用于从第二点记录数据，以及第二子仓段，其中数据输入从时间戳发生器连接。 筒仓写入控制逻辑响应于触发输出，在出现相应的触发输出时将表示每个第二点处的条件的数据和时间戳发生器的时间戳输出写入仓库的相应子仓段 使得作为触发输出的结果记录在筒仓组存储器中的每个条件与其相关联，表示触发输出的相对发生时间的时间戳计数。

公开(公告)号：US5210862A

公开(公告)日：1993-05-11

申请号：US455667

申请日：1989-12-22

Applicant: Douglas J. DeAngelis ,  Henry W. J. Maddox ,  Arthur Peters ,  Donald J. Rathbun ,  William L. Saltmarsh

Inventor： Douglas J. DeAngelis ,  Henry W. J. Maddox ,  Arthur Peters ,  Donald J. Rathbun ,  William L. Saltmarsh

IPC: G06F11/34 ,  G06F13/00

CPC classification number: G06F11/348 ,  G06F11/3466 ,  G06F11/349 ,  G06F11/3495

Abstract: A monitor device for selectively detecting and recording conditions at selected points within a system during operation, including a trigger enable memory for storing selectable trigger enabling codes wherein each code corresponds to a trigger signal representing the occurrence of a corresponding condition to be detected, a trigger generation device connected from first selected points and responsive to selected conditions thereupon for generating the trigger signals representing the occurrence of selected conditions, a trigger output device responsive to the enabling codes and the trigger signals for providing trigger outputs upon the occurrence of a trigger signal corresponding to a selected trigger enabling code, and a silo bank memory connected from second selected points and responsive to the trigger outputs for recording conditions present at the second points.

Abstract translation: 一种监视器装置，用于在操作期间选择性地检测和记录系统内的选定点处的条件，包括用于存储可选触发使能代码的触发允许存储器，其中每个代码对应于表示相应待检测条件的发生的触发信号，触发器 从第一选择点连接并且响应于所选择的条件，产生表示所选条件出现的触发信号，触发输出装置响应于使能码和触发信号，用于在触发信号发生时提供触发信号 到选定的触发启用代码，以及从第二选择点连接的仓库存储器，并响应于触发输出，用于记录存在于第二点的条件。