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129 条记录 (耗时 0.032 秒)

    IC layout optimization to improve yield
    7.
    发明授权
    IC layout optimization to improve yield 失效
    IC布局优化提高产量

    公开(公告)号：US07503020B2

    公开(公告)日：2009-03-10

    申请号：US11424922

    申请日：2006-06-19

    申请人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

    发明人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

    摘要翻译： 一种用于优化集成电路设计以提高制造产量的方法和服务。 本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。 本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

    Ethernet network implementing redundancy using a single category 5 cable
    8.
    发明授权
    Ethernet network implementing redundancy using a single category 5 cable 有权
    以太网使用单一类别5电缆实现冗余

    公开(公告)号：US07433302B2

    公开(公告)日：2008-10-07

    申请号：US11123325

    申请日：2005-05-04

    申请人： Robert J. Allen

    发明人： Robert J. Allen

    IPC分类号： H04J3/02 ,  G06F15/16

    CPC分类号： H04L12/40182 ,  H04L12/437 ,  Y10S370/908 ,  Y10S370/91

    摘要： A method for providing redundancy in a daisy chain local area network employing Category 5 cabling for connecting network devices uses the normally unused twisted wire pairs in the single Cat 5 cable connecting adjacent network devices. The method includes forming in each network device a passive signal path connecting pins of an upstream port associated with the normally unused twisted wire pairs of the Cat 5 cable to pins of a downstream port associated with the normally unused twisted wire pairs of the Cat 5 cable, forming loop back connections at the terminal network devices where the loop back connections connect the normally used twisted wire pairs to the normally unused twisted wire pairs of the Cat 5 cable connected to the terminal network devices, and implementing a Spanning Tree Protocol in each of the network devices for defining an active signal path through the local area network.

    摘要翻译： 在连接网络设备的采用5类布线的菊花链局域网中提供冗余的方法使用连接相邻网络设备的单个Cat 5电缆中通常使用的双绞线对。 该方法包括在每个网络设备中形成被动信号路径，该无源信号路径将与Cat5电缆的通常未使用的双绞线相关联的上游端口的引脚连接到与Cat 5电缆的通常未使用的双绞线对相关联的下游端口的引脚 在终端网络设备处形成环回连接，其中环回连接将常用的双绞线连接到连接到终端网络设备的Cat 5电缆的通常使用的双绞线对，并且在每个终端网络设备中实现生成树协议 用于定义通过局域网的活动信号路径的网络设备。

    Critical area computation of composite fault mechanisms using Voronoi diagrams
    9.
    发明授权
    Critical area computation of composite fault mechanisms using Voronoi diagrams 有权
    使用Voronoi图的复合故障机制的关键区域计算

    公开(公告)号：US07404159B2

    公开(公告)日：2008-07-22

    申请号：US11538913

    申请日：2006-10-05

    申请人： Robert J. Allen ,  Evanthia Papadopoulou ,  Mervyn Yee-Min Tan

    发明人： Robert J. Allen ,  Evanthia Papadopoulou ,  Mervyn Yee-Min Tan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.

    摘要翻译： 公开了一种在集成电路设计中确定与不同类型的故障机制相关联的关键区域的方法。 本发明通过为单个故障机制的关键区域构建单独的Voronoi图和基于各个Voronoi图的复合Voronoi图来实现。 本发明基于复合Voronoi图计算了集成电路设计复合故障机理的关键区域。

    Carbon-supported metal sulphide catalyst for electrochemical oxygen reduction
    10.
    发明申请
    Carbon-supported metal sulphide catalyst for electrochemical oxygen reduction 有权
    用于电化学氧还原的碳载金属硫化物催化剂

    公开(公告)号：US20080121520A1

    公开(公告)日：2008-05-29

    申请号：US11982799

    申请日：2007-11-05

    申请人： Andrea F. Gulla ,  Robert J. Allen

    发明人： Andrea F. Gulla ,  Robert J. Allen

    IPC分类号： C25B11/04 ,  B01J27/02

    CPC分类号： C25B11/0447 ,  B01J21/18 ,  B01J27/045 ,  H01M4/90 ,  H01M4/9083 ,  H01M4/923 ,  H01M4/926 ,  Y02E60/50

    摘要： An improved carbon supported-noble metal sulphide electrocatalyst suitable for being incorporated in gas-diffusion electrode structures, in particular in oxygen-reducing gas diffusion cathodes for aqueous hydrochloric acid electrolysis. The noble metal sulphide particles are monodispersed on the active carbon particles and the surface area ratio of noble metal sulphide particles to active carbon particles is at least 0.20.

    摘要翻译： 一种改进的碳负载型贵金属硫化物电催化剂，适用于掺入气体扩散电极结构中，特别是用于盐酸电解盐水的减氧气体扩散阴极中。 贵金属硫化物颗粒单分散在活性炭颗粒上，贵金属硫化物颗粒与活性炭颗粒的表面积比至少为0.20。