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公开(公告)号：US5331645A
公开(公告)日：1994-07-19
申请号：US54346
申请日：1993-04-26
CPC分类号： G06F11/1048 , H03M13/19
摘要： A pair of similar, 32-bit, error detection and correction devices, including a "lower 32-bit" device (210) and an "upper 32-bit" device (212) are configured as a 64-bit, error detection and correction system. When a (64-bit) word of data is being stored in memory, the lower 32-bit device (210) develops, on an inter-device bus (226), signals representing generation partial check bits. The upper 32-bit device (212) receives the partial check bits (226), and develops signals representing final check bits (236) for storage with the corresponding data word in memory (220 and 234). When a (64-bit) word of data is being retrieved from memory, from signals representing check bits retrieved from memory (222), the lower 32-bit device (210) generates on an inter-device bus (224), signals representing correction partial syndromes. From the correction partial syndromes (224), the upper 32-bit device (212) develops, on another inter-device bus (228), signals representing correction partial check bits; generates full syndromes; and corrects errors in the upper 32-bits of the corresponding retrieved data word (240). From the correction partial check bits (228) the lower 32-bit device (210) (also) generates full syndromes; and corrects errors in the corresponding lower 32-bits of the retrieved data word (230).
摘要翻译： 包括“低32位”设备（210）和“高32位”设备（212）的一对类似的32位错误检测和校正设备被配置为64位错误检测和 校正系统 当存储器中存储（64位）数据字时，下位32位器件（210）在器件间总线（226）上产生表示生成部分校验位的信号。 上部32位设备（212）接收部分校验位（226），并且产生表示用于与存储器（220和234）中的相应数据字存储的最终校验位（236）的信号。 当从存储器检索到（64位）数据字时，从表示从存储器（222）检索的校验位的信号中，下部32位器件（210）在器件间总线（224）上产生信号， 矫正部分综合征。 从校正部分综合征（224），上部32位装置（212）在另一个装置间总线（228）上形成表示校正部分校验位的信号; 产生完整的综合征; 并纠正对应检索的数据字（240）的高32位的错误。 从校正部分校验位（228），下部32位器件（210）（也）产生完整的校正子; 并纠正检索的数据字（230）的相应较低32位中的错误。
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公开(公告)号：US5581564A
公开(公告)日：1996-12-03
申请号：US629285
申请日：1990-12-18
申请人： Michael J. Miller , John R. Mick
发明人： Michael J. Miller , John R. Mick
IPC分类号： G06F11/22 , G01R31/3185 , H04B17/00
CPC分类号： G01R31/318572
摘要： A diagnostic circuit of the present invention has serial command input and output pins separate from its serial data input and output pins. In one embodiment, the diagnostic circuit has one command register and one data register, the data register receiving serially an input signal and providing serially an output signal through an input pin and an output pin respectively. In another embodiment, the diagnostic circuit has one command register and multiple data registers. Each data register including a zero-length register, can be separately addressed. In yet another embodiment, multiple serial data input and output pins are provided together with multiple data registers.
摘要翻译： 本发明的诊断电路具有与其串行数据输入和输出引脚分开的串行命令输入和输出引脚。 在一个实施例中，诊断电路具有一个命令寄存器和一个数据寄存器，数据寄存器串行地接收输入信号，并分别通过输入引脚和输出引脚提供输出信号。 在另一个实施例中，诊断电路具有一个命令寄存器和多个数据寄存器。 每个包括零长度寄存器的数据寄存器都可以单独寻址。 在另一个实施例中，多个串行数据输入和输出引脚与多个数据寄存器一起提供。
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公开(公告)号：US4760517A
公开(公告)日：1988-07-26
申请号：US920716
申请日：1986-10-17
申请人： Michael J. Miller , Danh Le Ngoc , John R. Mick
发明人： Michael J. Miller , Danh Le Ngoc , John R. Mick
CPC分类号： G06F15/7896
摘要： The combination of a seven-port random access memory (RAM) unit, a funnel shifter, a mask generator, an arithmetic logic unit (ALU), a merge logic unit, a number of multiplexers, and three bi-directional data buses are configured to form a thirty-two bit, cascadable, microprogrammable, bit-slice suitable for executing complex operations such as those which require that several operands be read from the memory unit, be rotated in the funnel shifter, be operated upon by the arithmetic logic unit, be merged in the merge logic unit, and the result be written back into the memory unit all in a single cycle.
摘要翻译： 配置七端口随机存取存储器（RAM）单元，漏斗移位器，掩码发生器，算术逻辑单元（ALU），合并逻辑单元，多个复用器和三个双向数据总线的组合 形成三十二位，可级联，可编程的位片，适用于执行复杂的操作，例如那些需要从存储器单元读取多个操作数的操作数，在漏斗移位器中旋转，由算术逻辑单元 ，合并到合并逻辑单元中，结果将在单个周期内写入存储器单元。
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公开(公告)号：US4782461A
公开(公告)日：1988-11-01
申请号：US623160
申请日：1984-06-21
CPC分类号： G06F11/3652 , G06F11/322 , G06F11/22 , G06F11/34
摘要： A logical grouping of facilities within a computer development system where said facilities include breakpoint control, trace control and memory, a plurality of VLSI emulators, a plurality of storage device emulators, a plurality of emulators for simulating program or microprogram storage, and may be selectively assigned to said grouping by a user. Said selectively assigned facilities are associated with a clock control and are used for the design, debugging and testing of computer systems.
摘要翻译： 计算机开发系统内的设备的逻辑分组，其中所述设施包括断点控制，跟踪控制和存储器，多个VLSI仿真器，多个存储设备仿真器，用于模拟程序或微程序存储的多个仿真器，并且可以是选择性地 被用户分配给所述分组。 所述选择性分配的设施与时钟控制相关联，并且用于计算机系统的设计，调试和测试。
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公开(公告)号：US09125646B2
公开(公告)日：2015-09-08
申请号：US13295186
申请日：2011-11-14
申请人： James A. Woodard, Jr. , Michael V. Sherrill , Jason R. Lesko , David T. Martin , Katherine J. Schmid , Michael J. Miller , Gary W. Knight , Richard F. Schwemberger , Atul M. Godbole
发明人： James A. Woodard, Jr. , Michael V. Sherrill , Jason R. Lesko , David T. Martin , Katherine J. Schmid , Michael J. Miller , Gary W. Knight , Richard F. Schwemberger , Atul M. Godbole
IPC分类号： A61B17/06 , A61B17/04 , A61B17/062 , A61B17/29
CPC分类号： A61B17/06004 , A61B17/0469 , A61B17/06066 , A61B17/062 , A61B2017/06009 , A61B2017/06019 , A61B2017/06023 , A61B2017/06047 , A61B2017/06052 , A61B2017/0609 , A61B2017/061 , A61B2017/2929
摘要： A surgical needle includes a pair of ends, a mid-region extending between the ends, and at least one grasping feature configured for grasping by a suturing instrument. An end of a suture is secured to the mid-region of the needle in a manner such that the end of the suture defines an oblique angle with at least part of the centerline defined by the mid-region of the needle. The end of the suture may be disposed in a hollow portion of the needle. The grasping feature may include a notch such as a scallop. The suture may be pivotally coupled with the needle via a ball or pin. The needle may have one or more sharp points. The sharp point may include three converging cutting edges, at least two planar surfaces bounded by the three cutting edges, and a rounded surface bounded by two of the three cutting edges.
摘要翻译： 外科用针包括一对端部，在端部之间延伸的中间区域，以及构造成用于通过缝合器械夹持的至少一个抓握部件。 缝合线的端部以这样的方式固定到针的中间区域，使得缝合线的端部限定与由针的中间区域限定的中心线的至少一部分的倾斜角度。 缝线的末端可以设置在针的中空部分中。 抓握功能可以包括诸如扇贝的凹口。 缝合线可以经由球或针与针枢转地联接。 针可能具有一个或多个尖锐点。 锐点可以包括三个会聚的切割边缘，由三个切割边界限定的至少两个平面，以及由三个切割边缘中的两个限定的圆形表面。
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公开(公告)号：US08368217B2
公开(公告)日：2013-02-05
申请号：US13541658
申请日：2012-07-03
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.
摘要翻译： 芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。 Tx端子彼此连续分组，并且作为组分离到包装的给定边缘，Rx端子被类似地分组并分离到包装的不同边缘。 Tx和Rx数据通道设置在封装的相应单层中，或者两者都被布置在封装的相同的单层中。 Rx端口和Tx端口位于封装的大致中心处，Tx和Rx端口设置在平分封装的轴的相应相对两侧。 分别从包装的第一边缘到包装的中心以及从包装的中心到包装的第二边缘的相同方向从芯片流接收和传输的数据信号。
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公开(公告)号：US20120267769A1
公开(公告)日：2012-10-25
申请号：US13541658
申请日：2012-07-03
申请人： Michael J. Miller , Mark Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark Baumann , Richard S. Roy
IPC分类号： H01L23/58
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.
摘要翻译： 芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。 Tx端子彼此连续分组，并且作为组分离到包装的给定边缘，Rx端子被类似地分组并分离到包装的不同边缘。 Tx和Rx数据通道设置在封装的相应单层中，或者两者都被布置在封装的相同的单层中。 Rx端口和Tx端口位于封装的大致中心处，Tx和Rx端口设置在平分封装的轴的相应相对两侧。 分别从包装的第一边缘到包装的中心以及从包装的中心到包装的第二边缘的相同方向从芯片流接收和传输的数据信号。
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公开(公告)号：US20120068339A1
公开(公告)日：2012-03-22
申请号：US12887298
申请日：2010-09-21
申请人： Michael J. Miller , Mark W. Baumann
发明人： Michael J. Miller , Mark W. Baumann
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L23/50 , G11C5/02 , H01L23/49838 , H01L24/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1434 , H01L2924/15174 , H01L2924/15311 , H01L2924/00 , H01L2224/0401
摘要： A packaged integrated circuit is presented for placement on a printed circuit board (PCB) layer providing power lines and data access channels. The packaged integrated circuit includes; a package substrate having data channels and power lines; a circuit substrate having functional components, wherein (a) the power lines and the data channels in the package substrate are coupled to the functional components of the substrate by conducting bumps, (b) the conducting balls coupling the data access channels in the PCB to the data channels in the package substrate are located along the edges of the package substrate; and (c) the conducting balls coupling the power lines in the PCB and the power lines in the package substrate are located in an interior portion of the package substrate. Also, an integrated circuit may further include a circuit substrate having active components, including a SerDes circuit at a center portion of the substrate.
摘要翻译： 提供封装的集成电路用于放置在提供电力线和数据访问通道的印刷电路板（PCB）层上。 封装的集成电路包括： 具有数据通道和电源线的封装基板; 具有功能部件的电路基板，其中（a）封装基板中的电源线和数据通道通过传导凸块而耦合到基板的功能部件，（b）将PCB中的数据访问通道耦合到的导电球到 封装衬底中的数据通道沿封装衬底的边缘定位; 和（c）将PCB中的电力线和封装衬底中的电力线耦合的导电球位于封装衬底的内部。 此外，集成电路还可以包括具有有源部件的电路基板，在基板的中心部分包括SerDes电路。
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公开(公告)号：US20120025397A1
公开(公告)日：2012-02-02
申请号：US12846763
申请日：2010-07-29
申请人： Michael J. Miller , Mark W. Baumann
发明人： Michael J. Miller , Mark W. Baumann
IPC分类号： H01L23/52
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
摘要翻译： 公开了一种用于高速半导体器件的芯片布局。 芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。 串行接口位于中心位置，以减少延迟，功率和传播延迟。 包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。
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10.发明授权公开(公告)号：US08005632B2
公开(公告)日：2011-08-23
申请号：US11936291
申请日：2007-11-07
IPC分类号： G01R19/00
CPC分类号： G01R35/00 , G01R31/024 , G01R31/2829
摘要： A method and article of manufacture are provided to monitor a sensing system operative to monitor electrical current in a transmission line between an electrical storage device and an electrical machine. The sensing system comprises first and second sensors, operative to monitor first and second ranges of electrical current. The method comprises determining outputs of the first and second sensors are valid, and comparing outputs of the first and second sensors when current is substantially zero. The method comprises comparing magnitudes of the outputs of the first and second sensors when the monitored electrical current, and monitoring polarity of each of the outputs of the first and second sensors.
摘要翻译： 提供了一种制造方法和监视感测系统，该感测系统可操作以监测电存储装置和电机之间的传输线路中的电流。 感测系统包括第一和第二传感器，用于监视第一和第二电流范围。 该方法包括确定第一和第二传感器的输出是有效的，并且当电流基本上为零时，比较第一和第二传感器的输出。 该方法包括：当监测的电流和第一和第二传感器的每个输出的监视极性时，比较第一和第二传感器的输出的幅度。
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