公开(公告)号：US06556162B2

公开(公告)日：2003-04-29

申请号：US09847661

申请日：2001-05-02

申请人： Michael James Brownlow ,  Graham Andrew Cairns ,  Catherine Rosinda Marie Armida Dachs ,  Hidehiko Yamashita ,  Yasushi Kubota ,  Hajime Washio

发明人： Michael James Brownlow ,  Graham Andrew Cairns ,  Catherine Rosinda Marie Armida Dachs ,  Hidehiko Yamashita ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： H03M166

CPC分类号： H03M1/682 ,  G09G3/3688 ,  G09G2310/0248 ,  G09G2310/027 ,  H03M1/687 ,  H03M1/765 ,  H03M1/804

摘要： A digital-to-analog converter includes a first converter stage 1 for converting the m most significant bits of a k bit input signal to upper and lower voltage limits VL and VH by selecting the appropriate low impedance reference voltages. A second converter stage 2 performs a linear conversion of the n least significant bits of the k bit input within the voltage range defined by the voltage limits VL and VH. A precharging circuit including switches SW1 and SW2 disconnects the stage 2 from the load CLOAD, which is charged to the voltage limit VL during the precharge phase. The load is subsequently disconnected from the voltage limit VL and connected to the output of the stage 2 to complete charging of the load CLOAD to the converter output voltage.

摘要翻译： 数模转换器包括第一转换器级1，用于通过选择合适的低阻抗参考电压将k位输入信号的m个最高有效位转换为上限和下限电压极限VL和VH。 第二转换器级2在由电压限制VL和VH限定的电压范围内执行k位输入的n个最低有效位的线性转换。 包括开关SW1和SW2的预充电电路从负载CLOAD断开级2，负载CLOAD在预充电阶段期间被充电到电压极限VL。 负载随后与电压限制VL断开并连接到级2的输出，以完成负载CLOAD到转换器输出电压的充电。

公开(公告)号：US06952244B2

公开(公告)日：2005-10-04

申请号：US10081917

申请日：2002-02-20

申请人： Graham Andrew Cairns ,  Catherine Rosinda Marie Armida Dachs ,  Michael James Brownlow ,  Yasuyoshi Kaise

发明人： Graham Andrew Cairns ,  Catherine Rosinda Marie Armida Dachs ,  Michael James Brownlow ,  Yasuyoshi Kaise

IPC分类号： G02F1/1368 ,  G02F1/1362 ,  G09F9/30 ,  G09F9/35 ,  G09G3/20 ,  G09G3/36 ,  H01L21/336 ,  H01L29/786 ,  G02F1/136 ,  H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： G02F1/136213 ,  G02F2001/136245 ,  G09G3/3648 ,  G09G2300/0809

摘要： An active matrix devise comprises an array of picture elements. Each picture element has an image element, such as an LCD cell (11) connected to a first storage capacitor 12 and arranged to be connected to a data line 4 by an thin film transistor 10 when activated by a scan signal on a scan line 6. A second storage capacitor 21 can be connected across the first capacitor 12 by means of another thin film transistor 20 when desired so as to increase the storage capacitance at the pixel.

摘要翻译： 有源矩阵设计包括一系列图像元素。 每个像素具有诸如连接到第一存储电容器12的LCD单元（11）的图像元件，并且被布置成当由扫描线6上的扫描信号激活时由薄膜晶体管10连接到数据线4 。 当需要时，第二存储电容器21可以通过另一薄膜晶体管20跨越第一电容器12连接，以增加像素处的存储电容。

公开(公告)号：US20080150924A1

公开(公告)日：2008-06-26

申请号：US12071529

申请日：2008-02-21

申请人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

发明人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

IPC分类号： G06F3/038 ,  H03K19/0175

CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G2310/0289 ,  G09G2330/021

摘要： There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

摘要翻译： 提供：第一逻辑运算电路，其使用高幅度逻辑信号执行逻辑运算; 具有负载电容的传输系统; 以及作为降压电平移位器的低压信号发生器，其将来自第一逻辑运算电路的输入高幅度逻辑信号变换为具有比高幅度逻辑信号更低的振幅的低幅度逻辑信号，以输出到 传输系统。 在该结构中，第一逻辑运算电路基于高幅度逻辑信号进行动作，因此没有故障，高速运转。 此外，引入负载电容的传输系统发送低幅度逻辑信号，因此抑制电力消耗的增加和不必要的辐射的发生。

公开(公告)号：US07358950B2

公开(公告)日：2008-04-15

申请号：US10145905

申请日：2002-05-16

申请人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

发明人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G2310/0289 ,  G09G2330/021

摘要： There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

摘要翻译： 提供：第一逻辑运算电路，其使用高幅度逻辑信号执行逻辑运算; 具有负载电容的传输系统; 以及作为降压电平移位器的低压信号发生器，其将来自第一逻辑运算电路的输入高幅度逻辑信号变换为具有比高幅度逻辑信号更低的振幅的低幅度逻辑信号，以输出到 传输系统。 在该结构中，第一逻辑运算电路基于高幅度逻辑信号进行动作，因此没有故障，高速运转。 此外，引入负载电容的传输系统发送低幅度逻辑信号，因此抑制电力消耗的增加和不必要的辐射的发生。

公开(公告)号：US07978169B2

公开(公告)日：2011-07-12

申请号：US12071529

申请日：2008-02-21

申请人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

发明人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G2310/0289 ,  G09G2330/021

摘要： There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

摘要翻译： 提供：第一逻辑运算电路，其使用高幅度逻辑信号执行逻辑运算; 具有负载电容的传输系统; 以及作为降压电平移位器的低压信号发生器，其将来自第一逻辑运算电路的输入高幅度逻辑信号变换为具有比高幅度逻辑信号更低的振幅的低幅度逻辑信号，以输出到 传输系统。 在该结构中，第一逻辑运算电路基于高幅度逻辑信号进行动作，因此没有故障，高速运转。 此外，引入负载电容的传输系统发送低幅度逻辑信号，因此抑制电力消耗的增加和不必要的辐射的发生。

公开(公告)号：US07042433B1

公开(公告)日：2006-05-09

申请号：US09567364

申请日：2000-05-09

申请人： Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Graham Andrew Cairns ,  Michael James Brownlow

发明人： Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Graham Andrew Cairns ,  Michael James Brownlow

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2310/0289

摘要： A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring. As a result, reduction of a parasitic capacitance of the wiring, reduction in the number of elements, reduction in the size of an amplitude of an input signal, etc. in the signal line driving circuit are attained.

摘要翻译： 信号线驱动电路包括具有多个移位电路的移位寄存器，每个移位电路将开始脉冲连续地移位到下一级，与时钟信号的定时同步。 在该信号线驱动电路中，基于两个相邻移位电路的输出脉冲，从与门输出移位脉冲。 同时，用于指定移位脉冲的脉冲宽度的宽度指定脉冲通过由移位脉冲控制其ON / OFF操作的晶体管输入。 逻辑运算电路对移位脉冲和宽度指定脉冲进行AND运算，并将运算结果输出到信号线。 当移位脉冲不起作用时，晶体管变为截止，使得将信号线发送宽度指定脉冲与信号线驱动电路断开，从而降低布线的容性负载。 结果，实现了信号线驱动电路中布线的寄生电容的减小，元件数目的减少，输入信号的幅度的减小等。

公开(公告)号：US07365727B2

公开(公告)日：2008-04-29

申请号：US10788161

申请日：2004-02-25

申请人： Masakazu Satoh ,  Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Michael James Brownlow ,  Graham Andrew Cairns

发明人： Masakazu Satoh ,  Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Michael James Brownlow ,  Graham Andrew Cairns

IPC分类号： G09G3/36

CPC分类号： G11C19/00 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2310/0283 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/28

摘要： A shift register is provided with a shift register section composed of a plurality of stages of flip-flops that operate in synchronization with a clock signal, and level shifters for boosting a start signal lower than a driving voltage and for applying the same to both ends of the shift register section, and the shift register is capable of switching the shift direction in accordance with the switching signal. The foregoing level shifters are current-driving-type level shifters that can operate even in the case where the transistor characteristics are inferior or in the case of fast operations, and that can carry out level shifting even with a start signal having a small amplitude. Furthermore, the foregoing level shifters are provided at both ends of the shift register section, respectively, and one of the same stops operating in accordance with a switching signal, so that consumed power should decrease. Consequently, there can be provided a shift register that is capable of shifting in two directions, that can normally operate even with an input signal having a small amplitude, and that therefore consumes less electric power.

摘要翻译： 移位寄存器具有移位寄存器部分，该移位寄存器部分由与时钟信号同步操作的多级触发器组成;以及电平移位器，用于升压低于驱动电压的启动信号，并将其施加到两端 的移位寄存器，并且移位寄存器能够根据切换信号切换移位方向。 上述电平移位器是电流驱动型电平移位器，即使在晶体管特性较差的情况下或者在快速操作的情况下也能够工作，并且即使利用具有小振幅的启动信号也能进行电平移位。 此外，上述电平移位器分别设置在移位寄存器部分的两端，并且其中一个电平移位器根据切换信号停止工作，从而消耗的功率应该减小。 因此，可以提供能够在两个方向上移位的移位寄存器，即使在具有小幅度的输入信号的情况下也能正常地进行操作，因此消耗较少的电力。

公开(公告)号：US06359491B1

公开(公告)日：2002-03-19

申请号：US09567757

申请日：2000-05-10

申请人： Graham Andrew Cairns ,  Michael James Brownlow ,  Yasushi Kubota ,  Hajime Washio

发明人： Graham Andrew Cairns ,  Michael James Brownlow ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： H03L500

CPC分类号： H03K19/018571

摘要： A voltage level shifter comprises complementary transistors T1, T2 connected between a supply line vdd and an inverting input !IN. The gates of the transistors T1 and T2 receive a shifted version of the direct input signal IN from a source-follower comprising the transistors T3 and T4.

摘要翻译： 电压电平移位器包括连接在电源线vdd和反相输入端IN之间的互补晶体管T1，T2。 晶体管T1和T2的栅极从包括晶体管T3和T4的源极跟随器接收直接输入信号IN的偏移形式。

公开(公告)号：US07339570B2

公开(公告)日：2008-03-04

申请号：US09851885

申请日：2001-05-09

申请人： Yasushi Kubota ,  Hajime Washio ,  Michael James Brownlow ,  Graham Andrew Cairns ,  Yasuyoshi Kaise ,  Kazuhiro Maeda

发明人： Yasushi Kubota ,  Hajime Washio ,  Michael James Brownlow ,  Graham Andrew Cairns ,  Yasuyoshi Kaise ,  Kazuhiro Maeda

IPC分类号： G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G5/005 ,  G09G5/006 ,  G09G2300/0456 ,  G09G2310/0205 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2320/0626 ,  G09G2330/021 ,  G09G2340/0428 ,  G09G2340/10 ,  G09G2340/12 ,  G09G2360/144 ,  H01L27/124 ,  H04N2007/145

摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.

摘要翻译： 图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。 不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。 可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。 此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。 因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。

公开(公告)号：US06909417B2

公开(公告)日：2005-06-21

申请号：US09578440

申请日：2000-05-25

申请人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

发明人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

IPC分类号： G11C19/00 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2330/021

摘要： A level shifter 13 is provided for each of SR flip flops F1 constituting a shift register 11. The level shifter 13 increases a voltage of a clock signal CK. This arrangement reduces a distance for transmitting a clock signal whose voltage has been increased, as compared with a construction in which a voltage of a clock signal is increased by a single level shifter and the signal is transmitted to each of the flip flops; consequently, a load capacity of the level shifter can be smaller. Furthermore, each of the level shifters is operated during a pulse output of the previous level shifter 13, and the operation is suspended at the end of the pulse output. Thus, the level shifters 13 can operate only when it is necessary to apply a clock signal CK to the corresponding SR flip flop F1. As a result, even when an amplitude of a clock signal is small, it is possible to reduce power consumption of the shift resister under normal operation.

摘要翻译： 为构成移位寄存器11的每个SR触发器F 1提供电平移位器13.电平移位器13增加时钟信号CK的电压。 与通过单个电平移位器增加时钟信号的电压并且将信号发送到每个触发器的结构相比，这种布置减少了用于传输电压已经增加的时钟信号的距离; 因此，电平转换器的负载能力可以更小。 此外，每个电平移位器在先前电平移位器13的脉冲输出期间操作，并且在脉冲输出结束时暂停操作。 因此，只有当需要对相应的SR触发器F 1施加时钟信号CK时，电平移位器13才能够工作。结果，即使当时钟信号的幅度小时，也可以降低功耗 的正常运行中的移位寄存器。