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公开(公告)号：US06603211B2
公开(公告)日：2003-08-05
申请号：US09784907
申请日：2001-02-15
IPC分类号： H01L23544
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method and system for providing an alignment mark for a thin layer in a semiconductor device is disclosed. The semiconductor device includes at least one alternative part having a first thickness greater than a second thickness of the thin layer. The method and system include providing the thin layer and providing the alignment mark for the thin layer in the at least one alternative part. The alignment mark has a depth that is greater than the second thickness of the thin layer. In one aspect, the method and system include providing a mask for the thin layer. The mask includes an alignment mark portion that covers the at least one alternative part and that is for providing the alignment mark. In this aspect, the method and system also include removing a portion of the at least one alternative part to provide the alignment mark in the at least one alternative part.
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2.发明授权Method and system for providing contacts with greater tolerance for misalignment in a flash memory 有权用于提供触点的方法和系统，其具有对于闪存中未对准的更大容限公开(公告)号：US06445051B1
公开(公告)日：2002-09-03
申请号：US09563797
申请日：2000-05-02
申请人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko , John Jianshi Wang , Michael K. Templeton , Lu You , Angela T. Hui
发明人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko , John Jianshi Wang , Michael K. Templeton , Lu You , Angela T. Hui
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/28273
摘要： A method and system for providing a plurality of contacts in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system include providing an etch stop layer covering the plurality of field insulating regions. The etch stop layer has an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions. The method and system also include providing an insulating layer covering the plurality of gate stacks, the plurality of field insulating regions and the etch stop layer. The method and system further include etching the insulating layer to provide a plurality of contact holes. The insulating layer etching step uses the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions. The method and system also include filling the plurality of contact holes with a conductor.
摘要翻译： 公开了一种用于在闪速存储器件中提供多个触点的方法和系统。 闪存器件包括多个栅极堆叠和与多个栅极堆叠的一部分相邻的多个场绝缘区域。 该方法和系统包括提供覆盖多个场绝缘区域的蚀刻停止层。 蚀刻停止层具有与多个场绝缘区域的场绝缘区蚀刻选择性不同的蚀刻选择性。 该方法和系统还包括提供覆盖多个栅极叠层，多个场绝缘区域和蚀刻停止层的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供多个接触孔。 绝缘层蚀刻步骤使用蚀刻停止层来确保绝缘蚀刻步骤不会蚀刻穿过多个场绝缘区域。 该方法和系统还包括用导体填充多个接触孔。
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3.发明授权Method for improved control of lines adjacent to a select gate using a mask assist feature 失效一种使用掩模辅助功能改进与选择门相邻的线的控制的方法公开(公告)号：US06495435B2
公开(公告)日：2002-12-17
申请号：US09788246
申请日：2001-02-15
申请人： Michael K. Templeton , Hao Fang , Maria C. Chan
发明人： Michael K. Templeton , Hao Fang , Maria C. Chan
IPC分类号： H01L2120
CPC分类号： H01L27/11521 , H01L21/76838 , H01L27/105 , H01L27/1052 , H01L27/115
摘要： A method and system for providing a plurality of lines in a semiconductor memory device is disclosed. The method and system include providing a semiconductor substrate, providing a plurality of lines and providing an adjacent feature. The plurality of lines includes an adjacent line adjacent to the adjacent feature. The each of the plurality of lines has a line width that is substantially the same for each of the plurality of lines. The plurality of lines is preferably formed utilizing a mask to print a physical mask for the plurality of lines and the adjacent feature. The mask includes a mask assist feature between at least a first polygon for the adjacent line and at least a second polygon for the adjacent feature. The mask assist feature has a size that is sufficiently large to affect the width of the adjacent line and that is sufficiently small to prevent a corresponding feature from being printed on the physical mask. The method and system also preferably include removing a second portion of the layer of material exposed by the pattern of the physical mask to form the plurality of lines.
摘要翻译： 公开了一种用于在半导体存储器件中提供多条线的方法和系统。 该方法和系统包括提供半导体衬底，提供多条线并提供相邻特征。 多条线包括与相邻特征相邻的相邻线。 多条线中的每条线具有对于多根线中的每条线基本相同的线宽度。 优选地，利用掩模形成多条线以打印多条线和相邻特征的物理掩模。 掩模包括用于相邻行的至少第一多边形和用于相邻特征的至少第二多边形之间的掩模辅助特征。 掩模辅助特征具有足够大的尺寸以影响相邻线的宽度，并且足够小以防止相应的特征被印刷在物理掩模上。 该方法和系统还优选地包括去除由物理掩模的图案暴露的材料层的第二部分以形成多条线。
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4.发明授权Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6110833A
公开(公告)日：2000-08-29
申请号：US33836
申请日：1998-03-03
IPC分类号： A61K38/00 , A61K38/30 , H01L21/8247 , H01L21/70
CPC分类号： H01L27/11521 , A61K38/30
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.
摘要翻译： 提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层。 然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。 蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。 多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。 绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙 第二存储单元。 此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。
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5.发明授权Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6043120A
公开(公告)日：2000-03-28
申请号：US33723
申请日：1998-03-03
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate. A masking layer is deposited or grown on the poly I layer, and at least a portion of the masking layer is etched so as to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. An interpoly dielectric layer and a second polysilicon (poly II) layer is formed over the poly I layer and insulator substantially free of abrupt changes in step height.
摘要翻译： 一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层。 在多晶硅层上沉积或生长掩模层，并且蚀刻掩模层的至少一部分，以便对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。 多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极电隔离。 在多层I层和绝缘体上形成多层介电层和第二多晶硅（poly II）层，绝缘体基本上没有台阶高度的突然变化。
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6.发明授权Memory cell structure for elimination of oxynitride (ONO) etch residue and polysilicon stringers 有权用于消除氧氮化物（ONO）蚀刻残留物和多晶硅桁架的记忆单元结构公开(公告)号：US06455888B1
公开(公告)日：2002-09-24
申请号：US09506298
申请日：2000-02-17
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , A61K38/30
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.
摘要翻译： 提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层。 然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。 蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。 多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。 绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙 第二存储单元。 此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。
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7.发明授权Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6030868A
公开(公告)日：2000-02-29
申请号：US33916
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.
摘要翻译： 一种制造第一存储单元的方法和具有彼此电隔离的浮动栅极的第二存储单元。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层，多晶硅层的部分用作第一和第二存储单元的未来浮动栅极。 在多晶硅层上形成多层介电层。 蚀刻至少一部分互电介质层以暴露多晶硅层的至少一部分，以便在多晶硅层的暴露部分的任一侧上对浮动栅极进行图案化。 多层I的暴露部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮动栅极与第二存储单元的浮置栅极电隔离。 形成基本上没有台阶高度突然变化的第二多晶硅（poly II）层。
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公开(公告)号：US07153364B1
公开(公告)日：2006-12-26
申请号：US10000208
申请日：2001-10-23
申请人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael K. Templeton
发明人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael K. Templeton
CPC分类号： H01L21/6715 , B05B15/50 , B05C11/08
摘要： The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.
摘要翻译： 本发明提供了一种用于分配头的虚拟分配抗蚀剂的系统和方法，同时减轻与虚拟分配过程相关的废物。 虚拟分配的抗蚀剂返回到被采集的储存器。 在基板应用之间，分配头可以被定位成将抗蚀剂分配到返回线中。 来自分配头的抗蚀剂的流动在分配头保持抗干燥。 通过将虚拟分配的抗蚀剂漏出到具有低体积的返回管线中，例如，可以减轻来自虚拟分配过程的废物。
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公开(公告)号：US07145653B1
公开(公告)日：2006-12-05
申请号：US09591017
申请日：2000-06-09
IPC分类号： G01N21/00
CPC分类号： G01N21/5907 , G01N15/0205 , G01N21/94 , G01N21/9501 , G01N2021/5961 , G01N2021/8411 , H01L22/10
摘要： A system and method is provided for monitoring and controlling the contaminant particle count contained in an aerosol during a photoresist coating and/or development process of a semiconductor. The monitoring system monitors the contaminate particle count present in the environment of the photoresist coating and/or development process, such as in a process chamber or a cup, enclosing the wafer during the process. The present invention employs in situ laser scattering or laser doppler anemometry techniques to detect the particle count level in the chamber or cup. A plurality of lasers and detectors can be positioned at different heights in or outside of a chamber or cup to facilitate detecting particles at different height levels. A laser could be used in conjunction with mirrors to provide a similar measurement. The particle count level can be used to compare with the defect level, so that it can be determined if a cleaner environment and/or process should be implemented.
摘要翻译： 提供了一种系统和方法，用于在半导体的光致抗蚀剂涂覆和/或显影过程期间监测和控制包含在气溶胶中的污染物颗粒数。 监测系统监测光致抗蚀剂涂层和/或显影过程环境中存在的污染颗粒数，例如在处理室或杯中，在处理过程中包围晶片。 本发明采用原位激光散射或激光多普勒血流计技术来检测腔室或杯子中的颗粒计数水平。 多个激光器和检测器可以位于室或杯内或室外的不同高度处，以便于检测不同高度水平的颗粒。 激光可以与镜子一起使用以提供类似的测量。 可以使用粒子计数水平与缺陷水平进行比较，以便可以确定是否应实施更清洁的环境和/或过程。
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公开(公告)号：US07078348B1
公开(公告)日：2006-07-18
申请号：US09893188
申请日：2001-06-27
IPC分类号： H01L21/302 , H01L21/3065
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76811 , H01L21/76813
摘要： One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.
摘要翻译： 本发明的一个方面涉及在单一蚀刻工艺中在绝缘层中制造双镶嵌图案的方法，该方法包括提供其上形成有至少一个绝缘层的晶片; 在所述至少一个绝缘层上沉积第一光致抗蚀剂层; 将第一图像图案化成第一光致抗蚀剂层; 固化第一图案化光致抗蚀剂层; 在所述第一图案化光致抗蚀剂层上沉积第二光致抗蚀剂层; 将第二图像图案化成第二光致抗蚀剂层; 以及在单次蚀刻工艺中同时蚀刻通过第一图案化光致抗蚀剂层和第二图案化光致抗蚀剂层的至少一个绝缘层。
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