公开(公告)号：US06603211B2

公开(公告)日：2003-08-05

申请号：US09784907

申请日：2001-02-15

申请人： Michael K. Templeton ,  Hao Fang ,  Maria C. Chan ,  King Wai Kelwin Ko

发明人： Michael K. Templeton ,  Hao Fang ,  Maria C. Chan ,  King Wai Kelwin Ko

IPC分类号： H01L23544

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and system for providing an alignment mark for a thin layer in a semiconductor device is disclosed. The semiconductor device includes at least one alternative part having a first thickness greater than a second thickness of the thin layer. The method and system include providing the thin layer and providing the alignment mark for the thin layer in the at least one alternative part. The alignment mark has a depth that is greater than the second thickness of the thin layer. In one aspect, the method and system include providing a mask for the thin layer. The mask includes an alignment mark portion that covers the at least one alternative part and that is for providing the alignment mark. In this aspect, the method and system also include removing a portion of the at least one alternative part to provide the alignment mark in the at least one alternative part.

公开(公告)号：US06448594B1

公开(公告)日：2002-09-10

申请号：US09539307

申请日：2000-03-30

申请人： Maria C. Chan ,  Hao Fang ,  Lu You ,  Mark S. Chang ,  King Wai Kelwin Ko

发明人： Maria C. Chan ,  Hao Fang ,  Lu You ,  Mark S. Chang ,  King Wai Kelwin Ko

IPC分类号： H01L2976

CPC分类号： H01L21/823468 ,  H01L21/823425 ,  Y10S257/90

摘要： In a first aspect of the present invention, a semiconductor device is disclosed. The semiconductor device comprises at least two gate stacks, each gate stack having two sides and oxide spacers on each of the two sides of each of the at least two gate stacks, wherein at least one of the oxide spacers is triangular shaped. In a second aspect of the present invention, a method and system for processing a semiconductor device is disclosed. The method and system for processing a semiconductor comprise forming at least two gate stacks over a semiconductor substrate, depositing an oxide layer over the at least two gate stacks, and etching the oxide layer to form at least one oxide spacer in between the at least two gate stacks, wherein the at least one oxide spacer is triangular shape. Through the use the present invention, the voids that are created in the semiconductor device during conventional semiconductor processing are eliminated. This is accomplished by creating oxide spacers having a triangular shape when etching the oxide layer to form the oxide spacer. By creating a triangular shaped oxide spacer, subsequent layers of material can be deposited over the oxide spacer without creating voids in the semiconductor device. Accordingly, as a result of the use of the present invention, the oxide spacers are strengthened, which increases the reliability of the semiconductor device.

摘要翻译： 在本发明的第一方面中，公开了一种半导体器件。 半导体器件包括至少两个栅极堆叠，每个栅极堆叠体具有在所述至少两个栅极堆叠中的每一个的两侧上的两个侧面和氧化物间隔物，其中至少一个氧化物间隔物是三角形的。 在本发明的第二方面中，公开了一种用于处理半导体器件的方法和系统。 用于处理半导体的方法和系统包括在半导体衬底上形成至少两个栅极叠层，在所述至少两个栅极堆叠上沉积氧化物层，以及蚀刻氧化物层以在至少两个栅极堆叠之间形成至少一个氧化物间隔物 栅堆叠，其中所述至少一个氧化物间隔物是三角形的。 通过使用本发明，消除了在常规半导体处理期间在半导体器件中产生的空隙。 这通过在蚀刻氧化物层以形成氧化物间隔物时形成具有三角形形状的氧化物间隔物来实现。 通过产生三角形氧化物间隔物，随后的材料层可沉积在氧化物间隔物上，而不会在半导体器件中产生空隙。 因此，作为使用本发明的结果，氧化物间隔物被加强，这增加了半导体器件的可靠性。

公开(公告)号：US06495435B2

公开(公告)日：2002-12-17

申请号：US09788246

申请日：2001-02-15

申请人： Michael K. Templeton ,  Hao Fang ,  Maria C. Chan

发明人： Michael K. Templeton ,  Hao Fang ,  Maria C. Chan

IPC分类号： H01L2120

CPC分类号： H01L27/11521 ,  H01L21/76838 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115

摘要： A method and system for providing a plurality of lines in a semiconductor memory device is disclosed. The method and system include providing a semiconductor substrate, providing a plurality of lines and providing an adjacent feature. The plurality of lines includes an adjacent line adjacent to the adjacent feature. The each of the plurality of lines has a line width that is substantially the same for each of the plurality of lines. The plurality of lines is preferably formed utilizing a mask to print a physical mask for the plurality of lines and the adjacent feature. The mask includes a mask assist feature between at least a first polygon for the adjacent line and at least a second polygon for the adjacent feature. The mask assist feature has a size that is sufficiently large to affect the width of the adjacent line and that is sufficiently small to prevent a corresponding feature from being printed on the physical mask. The method and system also preferably include removing a second portion of the layer of material exposed by the pattern of the physical mask to form the plurality of lines.

摘要翻译： 公开了一种用于在半导体存储器件中提供多条线的方法和系统。 该方法和系统包括提供半导体衬底，提供多条线并提供相邻特征。 多条线包括与相邻特征相邻的相邻线。 多条线中的每条线具有对于多根线中的每条线基本相同的线宽度。 优选地，利用掩模形成多条线以打印多条线和相邻特征的物理掩模。 掩模包括用于相邻行的至少第一多边形和用于相邻特征的至少第二多边形之间的掩模辅助特征。 掩模辅助特征具有足够大的尺寸以影响相邻线的宽度，并且足够小以防止相应的特征被印刷在物理掩模上。 该方法和系统还优选地包括去除由物理掩模的图案暴露的材料层的第二部分以形成多条线。

公开(公告)号：US06455888B1

公开(公告)日：2002-09-24

申请号：US09506298

申请日：2000-02-17

申请人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

发明人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  A61K38/30

摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.

摘要翻译： 提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层。 然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。 蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。 多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。 绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙 第二存储单元。 此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。

公开(公告)号：US6030868A

公开(公告)日：2000-02-29

申请号：US33916

申请日：1998-03-03

申请人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan ,  Mark T. Ramsbey

发明人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan ,  Mark T. Ramsbey

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.

摘要翻译： 一种制造第一存储单元的方法和具有彼此电隔离的浮动栅极的第二存储单元。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层，多晶硅层的部分用作第一和第二存储单元的未来浮动栅极。 在多晶硅层上形成多层介电层。 蚀刻至少一部分互电介质层以暴露多晶硅层的至少一部分，以便在多晶硅层的暴露部分的任一侧上对浮动栅极进行图案化。 多层I的暴露部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮动栅极与第二存储单元的浮置栅极电隔离。 形成基本上没有台阶高度突然变化的第二多晶硅（poly II）层。

公开(公告)号：US6110833A

公开(公告)日：2000-08-29

申请号：US33836

申请日：1998-03-03

申请人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

发明人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

IPC分类号： A61K38/00 ,  A61K38/30 ,  H01L21/8247 ,  H01L21/70

CPC分类号： H01L27/11521 ,  A61K38/30

摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.

摘要翻译： 提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层。 然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。 蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。 多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。 绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙 第二存储单元。 此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。

公开(公告)号：US6043120A

公开(公告)日：2000-03-28

申请号：US33723

申请日：1998-03-03

申请人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

发明人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate. A masking layer is deposited or grown on the poly I layer, and at least a portion of the masking layer is etched so as to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. An interpoly dielectric layer and a second polysilicon (poly II) layer is formed over the poly I layer and insulator substantially free of abrupt changes in step height.

摘要翻译： 一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层。 在多晶硅层上沉积或生长掩模层，并且蚀刻掩模层的至少一部分，以便对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。 多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极电隔离。 在多层I层和绝缘体上形成多层介电层和第二多晶硅（poly II）层，绝缘体基本上没有台阶高度的突然变化。

公开(公告)号：US06610580B1

公开(公告)日：2003-08-26

申请号：US09563179

申请日：2000-05-02

申请人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang ,  Mike Templeton

发明人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang ,  Mike Templeton

IPC分类号： H01L2176

CPC分类号： H01L27/11521 ,  H01L21/76205 ,  H01L21/76224 ,  H01L27/11517

摘要： In a first aspect of the present invention, a flash memory array is disclosed. The flash memory array comprises a substrate comprising active regions, wherein the active regions are defined by a layer of nitride, the layer of nitride including a top surface. The flash memory array further comprises shallow trenches in the substrate, each of the shallow trenches including a layer of oxide, the layer of oxide having a top surface, wherein the top surface of the layer of oxide and the top surface of the layer of nitride are on substantially the same plane and channel areas wherein the occurrences of polyl stringers in the channel areas is substantially reduced. In a second aspect of the present invention, a method and system for fabricating a flash memory array is disclosed. The method comprises the steps of providing a layer of nitride over a substrate, forming trenches in the substrate and then growing a layer of oxide in the trenches. Finally, the layer of oxide is polished back. Through the use of the preferred embodiment of the present invention, a shallow trench isolation process is implemented as opposed to LOCOS process, thereby reducing the occurrence of polyl stringers in the channel area. Accordingly, the occurrence of unwanted electrical shorting paths between the adjacent regions is substantially reduced.

摘要翻译： 在本发明的第一方面，公开了一种闪存阵列。 闪存阵列包括包含有源区的衬底，其中有源区由氮化物层限定，氮化物层包括顶表面。 闪存阵列还包括衬底中的浅沟槽，每个浅沟槽包括一层氧化物，氧化层具有顶表面，其中氧化层的顶表面和氮化层的顶表面 在基本相同的平面和通道区域上，其中通道区域中多边形桁条的出现被大大减少。 在本发明的第二方面中，公开了一种用于制造闪存阵列的方法和系统。 该方法包括以下步骤：在衬底上提供氮化物层，在衬底中形成沟槽，然后在沟槽中生长一层氧化物。 最后，氧化层被抛光。 通过使用本发明的优选实施例，与LOCOS工艺相反，实现了浅沟槽隔离工艺，从而减少了通道区域中多边形的发生。 因此，相邻区域之间不需要的电短路径的发生显着减少。

公开(公告)号：US06306706B1

公开(公告)日：2001-10-23

申请号：US09538922

申请日：2000-03-30

申请人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang

发明人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang

IPC分类号： H01L218247

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11531 ,  Y10T29/41

摘要： A method and system for fabricating a flash memory array comprising a core area and a periphery area is disclosed. The method and system comprises depositing a layer of poly2 over the core area and the periphery area, selectively etching the core area, and selectively etching the poly2 only in the periphery area wherein the occurrence of stringers is reduced. Through the use of the preferred embodiment of the present invention, the core and periphery areas are etched separately after the deposition of the poly2, thereby reducing the occurrence of stringers at the core/periphery interface. Accordingly, the occurrence of unwanted electrical shorting paths between the adjacent transistors is substantially reduced.

摘要翻译： 公开了一种用于制造包括芯区域和外围区域的闪存阵列的方法和系统。 该方法和系统包括在核心区域和外围区域上沉积多晶硅层2，选择性地蚀刻核心区域，并且仅在缩小桁条发生的周边区域中选择性地蚀刻聚二元体。 通过使用本发明的优选实施例，在沉积poly2之后分别蚀刻芯和外围区域，从而减少在芯/周边界面处的桁条的发生。 因此，相邻晶体管之间不需要的电短路径的发生显着减少。

公开(公告)号：US06352930B1

公开(公告)日：2002-03-05

申请号：US09814636

申请日：2001-03-22

申请人： Kathleen R. Early ,  Suzette K. Pangrle ,  Maria C. Chan ,  Lewis Shen

发明人： Kathleen R. Early ,  Suzette K. Pangrle ,  Maria C. Chan ,  Lewis Shen

IPC分类号： H01L21302

CPC分类号： H01L21/32139 ,  H01L21/3081 ,  H01L21/3143 ,  H01L21/31612 ,  Y10T428/259

摘要： In the manufacture of sub-0.35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically transparent at the deep ultraviolet wavelengths being used (248 nm), its thickness in combination with a preselected reflective silicon oxynitride thickness satisfies the zero reflectivity goal and, at the same time, is adequately thick to serve as a hard mask for self-aligned etch and self-aligned-source etch.

摘要翻译： 在使用深紫外光刻技术的0.35微米半导体的制造中，使用氮氧化硅顶部的二氧化硅双层作为底部抗反射涂层和用于光刻抗蚀剂的蚀刻硬掩模。 由于二氧化硅在使用的深紫外波长（248nm）下是光学透明的，其厚度与预选的反射氮氧化硅厚度相结合，满足零反射率目标，并且同时足够厚以用作硬 掩模，用于自对准蚀刻和自对准源蚀刻。