-
1.发明授权Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6110833A
公开(公告)日：2000-08-29
申请号：US33836
申请日：1998-03-03
IPC分类号： A61K38/00 , A61K38/30 , H01L21/8247 , H01L21/70
CPC分类号： H01L27/11521 , A61K38/30
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.
摘要翻译： 提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层。 然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。 蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。 多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。 绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙 第二存储单元。 此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。
-
2.发明授权Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6043120A
公开(公告)日：2000-03-28
申请号：US33723
申请日：1998-03-03
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate. A masking layer is deposited or grown on the poly I layer, and at least a portion of the masking layer is etched so as to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. An interpoly dielectric layer and a second polysilicon (poly II) layer is formed over the poly I layer and insulator substantially free of abrupt changes in step height.
摘要翻译： 一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层。 在多晶硅层上沉积或生长掩模层，并且蚀刻掩模层的至少一部分，以便对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。 多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极电隔离。 在多层I层和绝缘体上形成多层介电层和第二多晶硅（poly II）层，绝缘体基本上没有台阶高度的突然变化。
-
3.发明授权Memory cell structure for elimination of oxynitride (ONO) etch residue and polysilicon stringers 有权用于消除氧氮化物（ONO）蚀刻残留物和多晶硅桁架的记忆单元结构公开(公告)号：US06455888B1
公开(公告)日：2002-09-24
申请号：US09506298
申请日：2000-02-17
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , A61K38/30
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.
摘要翻译： 提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层。 然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。 蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。 多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。 绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙 第二存储单元。 此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。
-
4.发明授权Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6030868A
公开(公告)日：2000-02-29
申请号：US33916
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.
摘要翻译： 一种制造第一存储单元的方法和具有彼此电隔离的浮动栅极的第二存储单元。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层，多晶硅层的部分用作第一和第二存储单元的未来浮动栅极。 在多晶硅层上形成多层介电层。 蚀刻至少一部分互电介质层以暴露多晶硅层的至少一部分，以便在多晶硅层的暴露部分的任一侧上对浮动栅极进行图案化。 多层I的暴露部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮动栅极与第二存储单元的浮置栅极电隔离。 形成基本上没有台阶高度突然变化的第二多晶硅（poly II）层。
-
公开(公告)号：US06420702B1
公开(公告)日：2002-07-16
申请号：US09611641
申请日：2000-07-07
IPC分类号： H01J3728
CPC分类号： H01J37/28 , G01B15/00 , H01J2237/2814
摘要： An SEM measurement standard for measuring linewidths of 0.1 microns and below utilizes two different conducting materials in order to prevent charging effects. The top material is selected to use grain morphology to focus secondary electrons, and to obtain improved image contrast. The inventive standard is comprised of materials which are commonly used in semiconductor manufacturing and which do not cause contamination of fabrication facilities.
摘要翻译： 用于测量0.1微米及以下线宽的SEM测量标准使用两种不同的导电材料，以防止充电效应。 选择顶部材料以使用晶粒形态来聚焦二次电子，并获得改善的图像对比度。 本发明的标准由通常用于半导体制造并且不会引起制造设备污染的材料组成。
-
公开(公告)号：US08044387B1
公开(公告)日：2011-10-25
申请号：US10885959
申请日：2004-07-07
IPC分类号： H01L35/24
CPC分类号： H01L51/0591 , G11C13/0016 , G11C2213/71 , H01L27/285 , H01L51/0097
摘要： Disclosed are semiconductor memory devices containing a plastic substrate and at least one active device supported by the plastic substrate, the active device containing an organic semiconductor material. The semiconductor memory devices containing a plastic substrate may further contain a polymer dielectric and/or a conductive polymer.
摘要翻译： 公开了包含塑料基板和由塑料基板支撑的至少一个有源器件的半导体存储器件，该有源器件含有有机半导体材料。 包含塑料基板的半导体存储器件还可以包含聚合物电介质和/或导电聚合物。
-
7.发明授权Memory device with a selection element and a control line in a substantially similar layer 有权具有选择元件和控制线的存储器件在基本相似的层中公开(公告)号：US07696017B1
公开(公告)日：2010-04-13
申请号：US12141180
申请日：2008-06-18
IPC分类号： H01L21/82
CPC分类号： H01L27/1021 , H01L27/101
摘要： The invention facilitates manufacture of semiconductor memory components by reducing the number of layers required to implement a semiconductor memory device. The invention provides for a selection element to be formed in the same layer as one of the control lines (e.g. one of the wordline and bitline). In one embodiment of the invention, a diode is implemented as the selection element within the same layer as one of the control lines. Production of the selection element within the same layer as one of the wordline and bitline reduces problems associated with vertical stacking, increases device yield and reduces related production costs. The invention also provides an efficient method of producing memory devices with the selection element in the same layer as one of the control lines.
摘要翻译： 本发明有利于通过减少实现半导体存储器件所需的层数来制造半导体存储器组件。 本发明提供了一种选择元件，其形成在与控制线之一（例如字线和位线之一）相同的层中。 在本发明的一个实施例中，二极管被实现为与控制线之一在同一层内的选择元件。 生产作为字线和位线之一的同一层内的选择元件可减少与垂直堆叠相关的问题，提高了设备产量并降低了相关生产成本。 本发明还提供了一种生产存储器件的有效方法，其中选择元件与控制线之一在同一层中。
-
公开(公告)号：US20080175054A1
公开(公告)日：2008-07-24
申请号：US11724774
申请日：2007-03-16
CPC分类号： G11C16/3404 , G11C11/5671 , G11C16/3418 , G11C16/3422 , G11C16/3431 , G11C2029/0411
摘要： One embodiment of the invention relates to a method for refreshing a nonvolatile memory array. In the method, a threshold voltage of a multi-bit memory cell is analyzed to determine if it has drifted outside of a number of allowable voltage windows, wherein each allowable voltage windows corresponds to a different multi-bit value. If the threshold voltage of the cell has drifted outside of the number of allowable voltage states, then the cell is recovered by adjusting at least one voltage boundary of at least one of the number of allowable voltage states.
摘要翻译： 本发明的一个实施例涉及一种用于刷新非易失性存储器阵列的方法。 在该方法中，分析多位存储单元的阈值电压以确定其是否漂移在许多允许电压窗口之外，其中每个可允许电压窗对应于不同的多位值。 如果电池的阈值电压漂移在容许电压状态数之外，则通过调节至少一个容许电压状态数量的至少一个电压边界来恢复电池。
-
9.发明授权Protection of active layers of memory cells during processing of other elements 有权在处理其他元件期间保护存储器单元的有源层公开(公告)号：US07220642B2
公开(公告)日：2007-05-22
申请号：US10987262
申请日：2004-11-12
IPC分类号： H01L21/336
CPC分类号： H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： A method of fabricating an electronic structure by providing a conductive layer, providing a dielectric layer over the conductive layer, providing first and second openings through the dielectric layer, providing first and second conductive bodies in the first and second openings respectively and in contact with the conductive layer, providing a memory structure over the first conductive body, providing a protective element over the memory structure, and undertaking processing on the second conductive body.
摘要翻译： 一种通过提供导电层制造电子结构的方法，在导电层上提供电介质层，提供通过介电层的第一和第二开口，分别在第一和第二开口中提供第一和第二导电体，并与 在第一导电体上提供存储结构，在存储器结构上提供保护元件，并对第二导电体进行处理。
-
公开(公告)号：US06977389B2
公开(公告)日：2005-12-20
申请号：US10452877
申请日：2003-06-02
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , H01L27/28 , H01L51/0575
摘要： The present invention provides a planar polymer memory device that can operate as a non-volatile memory device. A planar polymer memory device can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and dielectric separate the electrodes. The method for forming a planar polymer memory device comprises at least one of forming a first electrode with an associated plug, forming a second electrode, forming a passive layer over the extension, depositing an organic polymer and patterning the organic polymer. The method affords integration of a planar polymer memory device into a semiconductor fabrication process. A thin film diode (TFD) can further be employed with a planar polymer memory device to facilitate programming. The TFD can be formed between the first electrode and the selectively conductive medium or the second electrode and the selectively conductive medium.
摘要翻译： 本发明提供一种能够作为非易失性存储器件操作的平面聚合物存储器件。 平面聚合物存储器件可以形成有两个或更多个电极和与一个电极相关联的电极延伸，其中选择性导电的介质和电介质分离电极。 用于形成平面聚合物记忆装置的方法包括以下步骤中的至少一种：形成具有相关塞子的第一电极，形成第二电极，在延伸部分上形成钝化层，沉积有机聚合物和图案化有机聚合物。 该方法将平面聚合物存储器件集成到半导体制造工艺中。 还可以使用薄膜二极管（TFD）与平面聚合物存储器件来促进编程。 可以在第一电极和选择性导电介质或第二电极和选择性导电介质之间形成TFD。
-
-
-
-
-
-
-
-
-
搜索结果
56 条记录 (耗时 0.028 秒)
