公开(公告)号：US06243787B1

公开(公告)日：2001-06-05

申请号：US09559352

申请日：2000-04-27

申请人： Michael Kagan ,  Diego Crupnicoff ,  Freddy Gabbay ,  Shimon Rottenberg

发明人： Michael Kagan ,  Diego Crupnicoff ,  Freddy Gabbay ,  Shimon Rottenberg

IPC分类号： G06F946

CPC分类号： H04L12/2854

摘要： A method and apparatus for conveying data over a packet-switching network. Data are received from a peripheral device for transmission via the network to a memory associated with a central processing unit (CPU), followed by an interrupt signal from the peripheral device associated with the data. One or more data packets containing the data are sent over the network to a host network interface serving the memory and the CPU, followed by an interrupt packet sent over the network to the host network interface. Responsive to the interrupt packet, an interrupt input of the CPU is asserted only after the one or more data packets have arrived at the host network interface.

摘要翻译： 一种用于通过分组交换网络传送数据的方法和装置。 从外围设备接收数据以经由网络传输到与中央处理单元（CPU）相关联的存储器，随后来自与数据相关联的外围设备的中断信号。 包含数据的一个或多个数据包通过网络发送到服务于存储器和CPU的主机网络接口，随后是通过网络发送到主机网络接口的中断包。 响应于中断包，只有在一个或多个数据包到达主机网络接口之后，才会断言CPU的中断输入。

公开(公告)号：US06978331B1

公开(公告)日：2005-12-20

申请号：US10070594

申请日：2000-09-07

申请人： Michael Kagan ,  Diego Crupnicoff ,  Freddy Gabbay ,  Shimon Rottenberg

发明人： Michael Kagan ,  Diego Crupnicoff ,  Freddy Gabbay ,  Shimon Rottenberg

IPC分类号： H04L1/00 ,  H04L12/24 ,  H04L12/40 ,  H04L12/46 ,  H04L12/56 ,  H04L12/66 ,  G06F13/00

CPC分类号： H04L12/66 ,  H04L1/0063 ,  H04L12/4604 ,  H04L12/4625 ,  H04L41/0213 ,  H04L41/06 ,  H04L2001/0092

摘要： A method and apparatus for conveying data over a packet-switching network (26). Data are received from a peripheral device (25) for transmission via the network to a memory (22) associated with a central processing unit (CPU) (21), followed by an interrupt signal from the peripheral device associated with the data. One or more data packets containing the data are sent over the network to a host network interface (32) serving the memory and the CPU, followed by an interrupt packet sent over the network to the host network interface. Responsive to the interrupt packet, an interrupt input of the CPU is asserted only after the one or more data packets have arrived at the host network interface.

摘要翻译： 一种用于通过分组交换网络（26）传送数据的方法和装置。 数据从外围设备（25）接收，用于经由网络传输到与中央处理单元（CPU）（21）相关联的存储器（22），随后是来自与数据相关联的外围设备的中断信号。 包含数据的一个或多个数据包通过网络发送到服务于存储器和CPU的主机网络接口（32），随后是通过网络发送到主机网络接口的中断包。 响应于中断包，只有在一个或多个数据包到达主机网络接口之后，才会断言CPU的中断输入。

公开(公告)号：US06438130B1

公开(公告)日：2002-08-20

申请号：US09892852

申请日：2001-06-28

申请人： Michael Kagan ,  Freddy Gabbay ,  Alon Webman ,  Diego Crupnicoff

发明人： Michael Kagan ,  Freddy Gabbay ,  Alon Webman ,  Diego Crupnicoff

IPC分类号： H04L1228

CPC分类号： H04L49/351

摘要： A device for switching packets in a network includes a switching core and a plurality of ports, coupled to pass the packets from one to another through the switching core. The ports include, with respect to each packet among the packets switched by the device, a receiving port, coupled to receive the packet from a packet source, and a destination port, to which the packet is passed for conveyance to a packet destination. The ports also include one or more cache memories, respectively associated with one or more of the ports, each of the cache memories being configured to hold a forwarding database cache for reference by the receiving port with which the cache memory is associated in determining the destination port of the packet.

摘要翻译： 用于在网络中切换分组的设备包括交换核心和多个端口，其被耦合以通过交换核心从一个到另一个传递分组。 对于由设备切换的分组中的每个分组，端口包括耦合以从分组源接收分组的接收端口和目的地端口，分组被传递到目的地端口以传送到分组目的地。 这些端口还包括分别与一个或多个端口相关联的一个或多个高速缓存存储器，每个高速缓存存储器被配置为保持转发数据库高速缓存以供高速缓冲存储器与其确定目的地所关联的接收端口相关联 端口的数据包。

公开(公告)号：US06922408B2

公开(公告)日：2005-07-26

申请号：US09758029

申请日：2001-01-10

申请人： Noam Bloch ,  Freddy Gabbay ,  Michael Kagan ,  Alon Webman ,  Diego Crupnicoff

发明人： Noam Bloch ,  Freddy Gabbay ,  Michael Kagan ,  Alon Webman ,  Diego Crupnicoff

IPC分类号： H04L1/00 ,  H04L12/24 ,  H04L12/40 ,  H04L12/46 ,  H04L12/56 ,  H04L12/66 ,  H04L12/28

CPC分类号： H04L12/66 ,  H04L12/4604 ,  H04L41/0213 ,  H04L41/06 ,  H04L47/10 ,  H04L47/30 ,  H04L47/39

摘要： A method for link-level flow control includes establishing a plurality of logical links over a physical link between a transmitting entity and a receiving entity in a network. Respective maximum limits of transmission credits are assigned to the logical links, the credits corresponding to space available to the links in a dynamically allocable portion of a receive buffer at the receiving entity, such that a sum of the maximum limits for all of the logical links corresponds to an amount of space substantially larger than a total volume of the space in the dynamically allocable portion of the receive buffer. Responsive to traffic from the transmitting entity to the receiving entity on a given one of the logical links, one or more of the credits are allocated to the given logical link when it is determined that a total of the credits allocated to the given logical link is no greater than the respective maximum limit, and that a total of the credits allocated to all of the logical links together corresponds to an allocated volume that is no greater than the total volume of the space in the dynamically allocable portion of the receive buffer. Transmission of data over the given logical link is controlled responsive to the allocated credits.

摘要翻译： 用于链路级流量控制的方法包括通过网络中的发送实体和接收实体之间的物理链路建立多个逻辑链路。 传输信用的最大限制被分配给逻辑链路，该信用对应于在接收实体处的接收缓冲器的动态可分配部分中的链路可用的空间，使得所有逻辑链路的最大限制的和 对应于基本上大于接收缓冲器的动态可分配部分中的空间的总体积的空间量。 响应于在给定的一个逻辑链路上从发送实体到接收实体的业务，当确定分配给给定逻辑链路的信用的总和是一个或多个信用被分配给给定的逻辑链路 不大于相应的最大限制，并且分配给所有逻辑链路的信用总数一起对应于不大于接收缓冲器的动态可分配部分中的空间的总体积的分配的卷。 通过给定的逻辑链路的数据传输是根据分配的信用来控制的。

公开(公告)号：US06668299B1

公开(公告)日：2003-12-23

申请号：US09655919

申请日：2000-09-06

申请人： Michael Kagan ,  Freddy Gabbay ,  Eilan Rabin ,  Haggai Telem

发明人： Michael Kagan ,  Freddy Gabbay ,  Eilan Rabin ,  Haggai Telem

IPC分类号： G06F1300

CPC分类号： H04L12/66 ,  H04L1/0061 ,  H04L1/0063 ,  H04L12/403 ,  H04L12/4604 ,  H04L41/0213 ,  H04L41/06 ,  H04L47/30 ,  H04L49/90 ,  H04L2001/0094 ,  Y10S370/911 ,  Y10S370/912

摘要： A bridge device, for coupling a parallel bus to a packet network, includes a bus interface adapter, coupled to the parallel bus so as to receive bus cycles from a master device on the bus. An outbound packet register, having a bus address in an address space of the bus, is adapted to store an outbound network address header and payload data written to the bus address of the register by the master device in one or more of the bus cycles received by the bus interface adapter. A network interface adapter is coupled to the network so as to transmit over the network an outbound packet containing the outbound network address header and payload data from the register, to a target device on the network specified by the network address header.

摘要翻译： 用于将并行总线耦合到分组网络的桥接设备包括耦合到并行总线的总线接口适配器，以便从总线上的主设备接收总线周期。 在总线的地址空间中具有总线地址的出站分组寄存器适于在接收到的一个或多个总线周期中存储由主设备写入到寄存器的总线地址的出站网络地址报头和有效载荷数据 由总线接口适配器。 网络接口适配器耦合到网络，以便通过网络将包含出站网络地址头和有效载荷数据的出站分组从寄存器传输到由网络地址头指定的网络上的目标设备。

公开(公告)号：US06516405B1

公开(公告)日：2003-02-04

申请号：US09475646

申请日：1999-12-30

申请人： Stephan J. Jourdan ,  Freddy Gabbay ,  Ronny Ronen ,  Adi Yoaz

发明人： Stephan J. Jourdan ,  Freddy Gabbay ,  Ronny Ronen ,  Adi Yoaz

IPC分类号： G06F945

CPC分类号： G06F9/30094 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3863

摘要： The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.

摘要翻译： 本发明涉及一种基于控制流推测（条件分支预测）的数据压缩的装置和方法。 由于条件分支结果基于实际数据值进行解析，条件分支预测提供了对数据值的潜在有价值的洞察。 如果相等的指令遇到分支，并且如果不是相等的指令预测该指令或分支，并且该指令被预测为未被使用，则本发明假设用于确定条件分支的两个操作数相等。 数据预测是安全的，因为数据错误预测是指条件分支错误预测，导致在包括数据错误预测的条件分支指令之后的指令的流水线刷新。

公开(公告)号：US08855129B2

公开(公告)日：2014-10-07

申请号：US11916711

申请日：2005-06-07

申请人： Boaz Shahar ,  Freddy Gabbay ,  Eyal Soha

发明人： Boaz Shahar ,  Freddy Gabbay ,  Eyal Soha

IPC分类号： H04L12/28 ,  H04L12/54 ,  H04L12/851 ,  H04L12/863 ,  H04L12/873 ,  H04L12/869

CPC分类号： H04L12/5693 ,  H04L47/245 ,  H04L47/50 ,  H04L47/522 ,  H04L47/58 ,  H04L47/6235

摘要： A method for transmitting packets, the method includes receiving multiple packets at multiple queues. The method is characterized by dynamically defining fixed priority queues and weighted fair queuing queues, and scheduling a transmission of packets in response to a status of the multiple queues and in response to the definition. A device for transmitting packets, the device includes multiple queues adapted to receive multiple packets. The device includes a circuit that is adapted to dynamically define fixed priority queues and weighted fair queuing queues out of the multiple queues and to schedule a transmission of packets in response to a status of the multiple queues and in response to the definition.

摘要翻译： 一种用于发送分组的方法，所述方法包括在多个队列处接收多个分组。 该方法的特征在于动态地定义固定优先级队列和加权公平排队队列，并且响应于多个队列的状态并响应于定义来调度分组的传输。 一种用于传输分组的设备，该设备包括适于接收多个分组的多个队列。 该设备包括适于在多个队列中动态地定义固定优先级队列和加权公平排队队列的电路，并响应于该定义响应于多个队列的状态来调度分组的传输。

公开(公告)号：US07284116B2

公开(公告)日：2007-10-16

申请号：US10307557

申请日：2002-12-02

申请人： Stephan J. Jourdan ,  Freddy Gabbay ,  Ronny Ronen ,  Adi Yoaz

发明人： Stephan J. Jourdan ,  Freddy Gabbay ,  Ronny Ronen ,  Adi Yoaz

IPC分类号： G06F9/34

CPC分类号： G06F9/30094 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3863

摘要： The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.

摘要翻译： 本发明涉及一种基于控制流推测（条件分支预测）的数据压缩的装置和方法。 由于条件分支结果基于实际数据值进行解析，条件分支预测提供了对数据值的潜在有价值的洞察。 如果相等的指令遇到分支，并且如果不是相等的指令预测该指令或分支，并且该指令被预测为未被使用，则本发明假设用于确定条件分支的两个操作数相等。 数据预测是安全的，因为数据错误预测是指条件分支错误预测，导致在包括数据错误预测的条件分支指令之后的指令的流水线刷新。

公开(公告)号：US20080198866A1

公开(公告)日：2008-08-21

申请号：US11916711

申请日：2005-06-07

申请人： Boaz Shahar ,  Freddy Gabbay ,  Eyal Soha

发明人： Boaz Shahar ,  Freddy Gabbay ,  Eyal Soha

IPC分类号： H04L12/56

CPC分类号： H04L12/5693 ,  H04L47/245 ,  H04L47/50 ,  H04L47/522 ,  H04L47/58 ,  H04L47/6235

摘要： A method for transmitting packets, the method includes receiving multiple packets at multiple queues. The method is characterized by dynamically defining fixed priority queues and weighted fair queuing queues, and scheduling a transmission of packets in response to a status of the multiple queues and in response to the definition. A device for transmitting packets, the device includes multiple queues adapted to receive multiple packets. The device includes a circuit that is adapted to dynamically define fixed priority queues and weighted fair queuing queues out of the multiple queues and to schedule a transmission of packets in response to a status of the multiple queues and in response to the definition.

摘要翻译： 一种用于发送分组的方法，所述方法包括在多个队列处接收多个分组。 该方法的特征在于动态地定义固定优先级队列和加权公平排队队列，并且响应于多个队列的状态并响应于定义来调度分组的传输。 一种用于传输分组的设备，该设备包括适于接收多个分组的多个队列。 该设备包括适于在多个队列中动态地定义固定优先级队列和加权公平排队队列的电路，并响应于该定义响应于多个队列的状态来调度分组的传输。

公开(公告)号：US5996060A

公开(公告)日：1999-11-30

申请号：US936738

申请日：1997-09-25

申请人： Avi Mendelson ,  Freddy Gabbay

发明人： Avi Mendelson ,  Freddy Gabbay

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/383 ,  G06F9/3455 ,  G06F9/3834

摘要： A processor and associated memory device that includes a fetcher for fetching instructions stored in the memory device. Each instruction constitutes either a value generating instruction or a non-value generating instruction. The processor further including a decoder for decoding the instructions, an issue unit for routing decoded instructions to an execution unit. The processor further having a predictor being responsive to a first set of instructions, from among the value generating instructions, for predicting, with respect to each one instruction in said first set of instructions, a predicted value that is determined on the basis of a prediction criterion which includes: (i) a previous value generated by the instruction; and (ii) at a stride.

摘要翻译： 一种处理器和相关联的存储器设备，其包括用于取出存储在存储器件中的指令的读取器。 每个指令构成值生成指令或非值生成指令。 处理器还包括用于解码指令的解码器，用于将解码的指令路由到执行单元的发布单元。 所述处理器进一步具有响应来自所述值生成指令的第一组指令的预测器，用于相对于所述第一组指令中的每个指令预测基于预测确定的预测值 标准包括：（i）由指令产生的先前值; 和（ii）一步一步。