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公开(公告)号：US06191620B1
公开(公告)日：2001-02-20
申请号：US09435064
申请日：1999-11-04
申请人： George McNeil Lattimore , Terry Lee Leasure , Younes John Lotfi , Robert Anthony Ross, Jr. , Gus Wai-Yan Yeung
发明人： George McNeil Lattimore , Terry Lee Leasure , Younes John Lotfi , Robert Anthony Ross, Jr. , Gus Wai-Yan Yeung
IPC分类号： G11C706
CPC分类号： H03K5/2481 , G11C7/062
摘要： A comparator circuit (40) includes a comparator network and a comparator enabling device (80) and may be integrated with a sense amplifier circuit (41). The comparator network is adapted to receive a complementary pair of reference data signals (B, B13) and a complementary pair of analog data signals (d1, d1b). An output of the comparator circuit (40) represents a comparison of the data represented by the reference data signals and the data represented by the analog data signals. The comparator output is generated in response to a comparator enable signal (SE) applied to the comparator enabling device (80) while the input data is applied to the comparator network. The comparator enable signal (SE) is applied at a time when the analog data signals (d1, d1b) have developed a minimum differential level.
摘要翻译： 比较器电路（40）包括比较器网络和比较器使能装置（80），并且可以与读出放大器电路（41）集成。 比较器网络适于接收互补的一对参考数据信号（B，B13）和互补的一对模拟数据信号（d1，d1b）。 比较器电路（40）的输出表示由参考数据信号表示的数据和由模拟数据信号表示的数据的比较。 响应于将比较器使能信号（SE）施加到比较器使能装置（80）而将输入数据施加到比较器网络而产生比较器输出。 当模拟数据信号（d1，d1b）产生最小差分电平时，施加比较器使能信号（SE）。
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公开(公告)号：US06915385B1
公开(公告)日：2005-07-05
申请号：US09364449
申请日：1999-07-30
CPC分类号： G06F12/0802 , G06F12/04 , Y02D10/13
摘要： An apparatus and method for unaligned cache reads is implemented. Data signals on a system bus are remapped into a cache line wherein a plurality of data values to be read from the cache are output in a group-wise fashion. The remapping defines a grouping of the data values in the cache line. A multiplexer is coupled to each group of storage units containing the data values, wherein a multiplexer input is coupled to each storage unit in the corresponding group. A logic array coupled to each MUX generates a control signal for selecting the data value output from each MUX. The control signal is generated in response to the read address which is decoded by each logic array.
摘要翻译： 实现了非对齐缓存读取的装置和方法。 将系统总线上的数据信号重新映射到高速缓存行中，其中将以分组方式输出要从高速缓存读取的多个数据值。 重映射定义了缓存行中数据值的分组。 多路复用器耦合到包含数据值的每组存储单元，其中多路复用器输入耦合到相应组中的每个存储单元。 耦合到每个MUX的逻辑阵列产生用于选择从每个MUX输出的数据值的控制信号。 响应于由每个逻辑阵列解码的读地址产生控制信号。
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3.发明授权Memory system having a unidirectional bus and method for communicating therewith 失效具有单向总线的存储器系统和与其通信的方法公开(公告)号：US06195280B1
公开(公告)日：2001-02-27
申请号：US09521352
申请日：2000-03-09
IPC分类号： G11C506
CPC分类号： G11C7/1048 , G11C7/12 , G11C7/18
摘要： A memory and a method for communicating therewith are implemented having a unidirectional write bus for writing to memory cells within a plurality of memory cell groups. Local bitlines associated with each of the memory cell groups communicate write data to the associated memory cell. Global bitlines coupled to all of the memory cells are decoupled from the local bitlines during a write operation. Following a write operation the local bitlines are restored by a precharge operation during which the global and local bitlines are also decoupled.
摘要翻译： 实现了与其通信的存储器和方法，其具有用于写入多个存储单元组内的存储单元的单向写总线。 与每个存储器单元组相关联的本地位线将写入数据传送到相关联的存储器单元。 耦合到所有存储器单元的全局位线在写操作期间与本地位线分离。 在写操作之后，通过预充电操作来恢复局部位线，在此期间，全局和本地位线也被去耦。
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4.发明授权Memory system having a unidirectional bus and method for communicating therewith 失效具有单向总线的存储器系统和与其通信的方法
公开(公告)号：US6081458A
公开(公告)日：2000-06-27
申请号：US140368
申请日：1998-08-26
CPC分类号： G11C7/1048 , G11C7/12 , G11C7/18
摘要： A memory and a method for communicating therewith are implemented having a unidirectional write bus for writing to memory cells within a plurality of memory cell groups. Local bitlines associated with each of the memory cell groups communicate write data to the associated memory cell. Global bitlines coupled to all of the memory cells are decoupled from the local bitlines during a write operation. Following a write operation the local bitlines are restored by a precharge operation during which the global and local bitlines are also decoupled.
摘要翻译： 实现了与其通信的存储器和方法，其具有用于写入多个存储单元组内的存储单元的单向写总线。 与每个存储器单元组相关联的本地位线将写入数据传送到相关联的存储器单元。 耦合到所有存储器单元的全局位线在写操作期间与本地位线分离。 在写操作之后，通过预充电操作来恢复局部位线，在此期间，全局和本地位线也被去耦。
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5.发明授权Memory in a data processing system having improved performance and method therefor 失效具有改进的性能和方法的数据处理系统中的存储器
公开(公告)号：US6058065A
公开(公告)日：2000-05-02
申请号：US82540
申请日：1998-05-21
CPC分类号： G11C7/18
摘要： A memory array is modified by segmenting the total length of a bitline into smaller bitline sections referred to as local bitlines. Included is an additional bitline into the array for every bitline that has been segmented. This new bitline is referred to as the global bitline. After segmentation, the array appears as several smaller sub-arrays; each sub-array has fewer cells per segmentation (local bitline) than the sum total of cells along the more traditional non-segmented bitline approach. These smaller sub-arrays (local bitline segmentations) are independent of one another and only one sub-array can be accessed per memory request (read/write). The reduced length and cell count per local bitline within each sub-array substantially reduces the total bitline capacitance (e.g., diffusion capacitance) discharged by a single memory cell during a read operation. Reducing bitline capacitance results in faster signal development and restore time on the bitline; thus, several smaller sub-arrays can be cycled much faster than a single large array.
摘要翻译： 通过将位线的总长度分割成称为本地位线的更小的位线部分来修改存储器阵列。 包括的是对于已经分段的每个位线，数组中都有一个位线。 这个新的位线被称为全局位线。 分割后，阵列显示为几个较小的子阵列; 每个子阵列比沿着更传统的非分段位线方法的细胞的总和小，每个分割（局部位线）具有更少的细胞。 这些较小的子阵列（本地位线分割）彼此独立，并且每个存储器请求（读/写）只能访问一个子阵列。 每个子阵列中的每个局部位线的减小的长度和单元计数基本上减少了在读取操作期间由单个存储器单元放电的总位线电容（例如，扩散电容）。 减少位线电容会导致更快的信号发展和位线恢复时间; 因此，几个较小的子阵列可以循环比单个大阵列快得多。
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公开(公告)号：US5982692A
公开(公告)日：1999-11-09
申请号：US905000
申请日：1997-08-01
CPC分类号： G11C7/18 , G11C7/1048 , G11C7/12
摘要： A method and apparatus is provided for implementing a memory cell array having a performance-improved critical read path using a boost amplifier configuration. The memory bit line is broken into small segments with a boost amplifier and the bit line is connected to the input of the amplifier. The output of the amplifier drives the global bit line. The amplifier is turned "on" during a "read" and turned "off" during a "write". During a read, one memory cell within one array segment is turned on. The memory cell drives the differential signal on to the local bit line pair. Also during a read, the boost amplifier which attaches to that local bit line is enabled. The boost amplifier amplifies the input signal (local bit line pair) and drives that signal on to the global bit line. Since the bit line is broken into small segments with boost amplifiers, there are many boost amplifiers attached on the global bit line. When enough signal is developed on the global bit line pair, the global sense amplifier is turned on. The bit line is thus quickly pulled to ground thereby significantly improving performance for the critical read path.
摘要翻译： 提供了一种用于实现具有使用升压放大器配置的性能改善的关键读取路径的存储单元阵列的方法和装置。 存储器位线用升压放大器分成小段，位线连接到放大器的输入。 放大器的输出驱动全局位线。 在“读取”期间，放大器“打开”并在“写入”期间关闭。 在读取期间，一个数组段内的一个存储单元被导通。 存储单元将差分信号驱动到本地位线对上。 此外，在读取期间，启用与本地位线相连的升压放大器。 升压放大器放大输入信号（局部位线对）并将该信号驱动到全局位线。 由于利用升压放大器将位线分解成小段，所以在全局位线上附加了许多升压放大器。 当在全局位线对上产生足够的信号时，全局读出放大器被打开。 因此，位线被快速拉到地，从而显着提高关键读路径的性能。
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公开(公告)号：US5877976A
公开(公告)日：1999-03-02
申请号：US959478
申请日：1997-10-28
摘要： An improved topology for multi-port memory cell layouts in which two or more bitline pairs are required for data transfers is provided. Bitlines are displaced vertically, rather than horizontally. Such vertical spacing provides improved silicon density while reducing bitline capacitance of a memory cell. Additionally, the use of vertically separated bitline pairs allows traditional transitional phase relationships between multi-port operations in multi-port memory implementations. To nullify any sensitivity to an overlapping restore operation, this improved topology includes cross-coupled ports.
摘要翻译： 提供了一种用于多端口存储器单元布局的改进的拓扑，其中需要两个或更多位线对来进行数据传输。 位线垂直位移，而不是水平位移。 这种垂直间隔提供了改进的硅密度，同时降低了存储单元的位线电容。 另外，使用垂直分离的位线对允许在多端口存储器实现中的多端口操作之间的传统的过渡相位关系。 为了消除对重复恢复操作的任何敏感性，该改进的拓扑包括交叉耦合端口。
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公开(公告)号：US5963486A
公开(公告)日：1999-10-05
申请号：US100354
申请日：1998-06-19
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/065 , G11C11/4096 , G11C7/1048 , G11C7/12
摘要： A bit switch circuit (10) includes an amplifier stage (11) and a plurality of input stages (23,33,43,53). Each input stage (23,33,43,53) is connected to receive as inputs the signals applied to a bit line pair associated with a memory array. Each input stage (23,33,43,53) is also associated with a common node (24,34,44,54), and a select transistor (T4, T5, T6, T7). Each select transistor (T4, T5, T6, T7) responds to a select input signal to couple the respective common node (24,34,44,54) to ground. This allows the sense amplifier (11) to respond to the data signals on the bit line pair (20,21,30,31,40,41,50,51) associated with the respective input stage (23,33,43,53).
摘要翻译： 位开关电路（10）包括放大器级（11）和多个输入级（23,33,43,53）。 每个输入级（23,33,43,53）被连接以接收施加到与存储器阵列相关联的位线对的信号作为输入。 每个输入级（23,33,43,53）也与公共节点（24,34,44,54）和选择晶体管（T4，T5，T6，T7）相关联。 每个选择晶体管（T4，T5，T6，T7）响应选择输入信号以将相应的公共节点（24,34,44,54）耦合到地。 这允许读出放大器（11）响应与相应输入级（23,33,43,53）相关联的位线对（20,21,30,31,40,41,50,51）上的数据信号 ）。
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9.发明授权Data processing system and method for generating memory control signals with clock skew tolerance 失效用于产生具有时钟偏差容限的存储器控制信号的数据处理系统和方法
公开(公告)号：US5870349A
公开(公告)日：1999-02-09
申请号：US959653
申请日：1997-10-28
IPC分类号： G11C7/10 , G11C11/412 , G11C7/00
CPC分类号： G11C7/1075 , G11C11/412
摘要： The data processing system of the present invention implements a multi-port memory cell, wherein the port functions are divided based on a timing cycle in which they may be accessed. For example, in one case, a first port may be utilized only for read operations and accessed only during a first portion of the timing cycle. Similarly, a second port may be used for read or write operations a and may be accessed only during a second portion of the timing cycle. To ensure that the multi-port memory cell functions correctly, both ports should not be accessed simultaneously. A circuit and method are implemented to ensure that both ports are not accessed simultaneously by implementing a delay function in a unique and useful manner.
摘要翻译： 本发明的数据处理系统实现了一个多端口存储单元，其中端口功能基于它们可被访问的定时周期被划分。 例如，在一种情况下，第一端口可以仅用于读取操作，并且仅在定时周期的第一部分期间被访问。 类似地，第二端口可以用于读取或写入操作a，并且可以仅在定时周期的第二部分期间被访问。 为了确保多端口存储单元功能正常，两个端口都不应同时访问。 实现电路和方法以通过以独特且有用的方式实现延迟功能来确保两个端口不被同时访问。
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10.发明授权Data processing system and method for implementing a multi-port memory cell 失效用于实现多端口存储单元的数据处理系统和方法
公开(公告)号：US5956286A
公开(公告)日：1999-09-21
申请号：US958559
申请日：1997-10-28
CPC分类号： G11C8/16
摘要： The data processing system of the present invention implements a multi-port memory cell, wherein the port functions are divided based on a timing cycle in which they may be accessed. For example, in one case, a first port may be utilized only for read operations and accessed only during a first portion of the timing cycle. Similarly, a second port may be used for read or write operations and may be accessed only during a second portion of the timing cycle. To ensure that the multi-port memory cell functions correctly, both ports should not be accessed simultaneously. A circuit and method are implemented to ensure that both ports are not accessed simultaneously by implementing a delay function in a unique and useful manner.
摘要翻译： 本发明的数据处理系统实现了一个多端口存储单元，其中端口功能基于它们可被访问的定时周期被划分。 例如，在一种情况下，第一端口可以仅用于读取操作，并且仅在定时周期的第一部分期间被访问。 类似地，第二端口可以用于读取或写入操作，并且可以仅在定时周期的第二部分期间被访问。 为了确保多端口存储单元功能正常，两个端口都不应同时访问。 实现电路和方法以通过以独特且有用的方式实现延迟功能来确保两个端口不被同时访问。
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