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    INTEGRATED CIRCUIT HAVING A MEMORY ARRAY
    2.
    发明申请
    INTEGRATED CIRCUIT HAVING A MEMORY ARRAY 审中-公开
    具有存储阵列的集成电路

    公开(公告)号：US20080205179A1

    公开(公告)日：2008-08-28

    申请号：US11680305

    申请日：2007-02-28

    申请人： Michael Markert ,  Michael Angerbauer ,  Corvin Liaw

    发明人： Michael Markert ,  Michael Angerbauer ,  Corvin Liaw

    IPC分类号： G11C7/12

    CPC分类号： G11C13/0011 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009

    摘要： An integrated circuit having a memory array and a method for reducing sneak current in a memory array is disclosed.One embodiment provides a memory array including a plurality of storage devices arranged as a plurality of rows and a plurality of columns. A first voltage is applied to a particular word line to select a column of storage devices. A second voltage is applied to a particular bit line of the plurality of bit lines to select a row of storage devices, and the second voltage is applied to each of further lines except for a further line being connected to the storage devices of the selected column.

    摘要翻译： 公开了一种具有存储器阵列的集成电路和用于减少存储器阵列中的潜行电流的方法。 一个实施例提供一种存储器阵列，其包括被布置为多行和多列的多个存储装置。 将第一电压施加到特定字线以选择一列存储设备。 第二电压被施加到多个位线的特定位线以选择一行存储装置，并且第二电压被施加到每个其它线，除了连接到所选列的存储装置的另外的线 。

    Method of Operating an Integrated Circuit, Integrated Circuit, and Memory Module
    6.
    发明申请
    Method of Operating an Integrated Circuit, Integrated Circuit, and Memory Module 有权
    操作集成电路，集成电路和存储器模块的方法

    公开(公告)号：US20090021976A1

    公开(公告)日：2009-01-22

    申请号：US11778549

    申请日：2007-07-16

    申请人： Corvin Liaw ,  Michael Angerbauer ,  Peter Schroegmeier

    发明人： Corvin Liaw ,  Michael Angerbauer ,  Peter Schroegmeier

    IPC分类号： G11C11/00

    CPC分类号： G11C13/00 ,  G11C5/02 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/79

    摘要： A method of operating an integrated circuit is provided. The integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first input terminal and a second input terminal; a signal line being connected to the plurality of resistivity changing memory cells, the at least one resistivity changing reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal. The method includes: closing the switching element; supplying a first voltage to the first input terminal via the signal line and the switching element; opening the switching element; supplying a second voltage to the second input terminal via the signal line; and comparing the first voltage and the second voltage using the voltage comparator, wherein the first voltage represents a memory state of a resistivity changing memory cell, and the second voltage is a reference voltage which represents a memory state of a resistivity changing reference cell, or vice versa.

    摘要翻译： 提供一种操作集成电路的方法。 集成电路包括多个电阻率变化存储单元和至少一个电阻率变化参考单元; 电压比较器，包括第一输入端子和第二输入端子; 信号线连接到所述多个电阻率变化存储单元，所述至少一个电阻率变化参考单元和所述第二输入端子; 以及将第一输入端子连接到第二输入端子的开关元件。 该方法包括：闭合开关元件; 经由所述信号线和所述开关元件向所述第一输入端提供第一电压; 打开开关元件; 经由信号线向第二输入端提供第二电压; 以及使用所述电压比较器来比较所述第一电压和所述第二电压，其中所述第一电压表示电阻率变化存储单元的存储状态，所述第二电压是表示电阻率变化参考单元的存储状态的参考电压，或 反之亦然。

    Integrated circuit with Resistivity changing memory cells and methods of operating the same
    7.
    发明授权
    Integrated circuit with Resistivity changing memory cells and methods of operating the same 有权
    具有电阻率变化的存储单元的集成电路及其操作方法

    公开(公告)号：US07706201B2

    公开(公告)日：2010-04-27

    申请号：US11778549

    申请日：2007-07-16

    申请人： Corvin Liaw ,  Michael Angerbauer ,  Peter Schroegmeier

    发明人： Corvin Liaw ,  Michael Angerbauer ,  Peter Schroegmeier

    IPC分类号： G11C7/02

    CPC分类号： G11C13/00 ,  G11C5/02 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/79

    摘要： An integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first and second input terminals; a signal line connected to the memory cells, the reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal. A method of operating the integrated circuit includes closing the switching element; supplying a first voltage to the first input terminal via the signal line and the switching element; opening the switching element; supplying a second voltage to the second input terminal via the signal line; and comparing the first and second voltages using the voltage comparator, wherein the first voltage represents a memory state of a memory cell, and the second voltage is a reference voltage which represents a memory state of a reference cell, or vice versa.

    摘要翻译： 集成电路包括多个电阻率变化存储单元和至少一个电阻率变化参考单元; 电压比较器，包括第一和第二输入端子; 连接到存储器单元，参考单元和第二输入端子的信号线; 以及将第一输入端子连接到第二输入端子的开关元件。 一种操作集成电路的方法包括：关闭开关元件; 经由所述信号线和所述开关元件向所述第一输入端提供第一电压; 打开开关元件; 经由信号线向第二输入端提供第二电压; 以及使用所述电压比较器来比较所述第一和第二电压，其中所述第一电压表示存储器单元的存储状态，并且所述第二电压是表示参考单元的存储器状态的参考电压，反之亦然。

    Memory circuit having a resistive memory cell and method for operating such a memory circuit
    9.
    发明申请
    Memory circuit having a resistive memory cell and method for operating such a memory circuit 审中-公开
    具有电阻存储单元的存储器电路和用于操作这种存储器电路的方法

    公开(公告)号：US20070195580A1

    公开(公告)日：2007-08-23

    申请号：US11361062

    申请日：2006-02-23

    申请人： Heinz Hoenigschmid ,  Corvin Liaw ,  Milena Dimitrova ,  Michael Angerbauer

    发明人： Heinz Hoenigschmid ,  Corvin Liaw ,  Milena Dimitrova ,  Michael Angerbauer

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C11/16 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/76 ,  G11C2213/79

    摘要： The invention relates to a memory circuit comprising a resistive memory cell having a selection transistor and a resistive memory element connected in series, wherein the resistive memory element is coupled to a plate potential; and a control circuit to control the selection transistor by means of an activation signal a pre-charge circuit coupled with a node between the selection transistor and the resistive memory element and to apply a compensation potential to the node; wherein the control circuit controls the pre-charge circuit so that a compensation potential is applied to the node prior to a level transition of the activation signal.

    摘要翻译： 本发明涉及一种包括具有串联连接的选择晶体管和电阻性存储元件的电阻式存储单元的存储器电路，其中该电阻式存储器元件耦合到一个电位电位; 以及控制电路，通过激活信号控制所述选择晶体管，所述预充电电路与所述选择晶体管和所述电阻性存储器元件之间的节点耦合，并向所述节点施加补偿电位; 其中所述控制电路控制所述预充电电路，使得在所述激活信号的电平转换之前将补偿电位施加到所述节点。