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    High-K/metal gate stack using capping layer methods, IC and related transistors
    3.
    发明授权
    High-K/metal gate stack using capping layer methods, IC and related transistors 有权
    高K /金属栅极堆叠采用封盖层法，IC及相关晶体管

    公开(公告)号：US09236314B2

    公开(公告)日：2016-01-12

    申请号：US13433659

    申请日：2012-03-29

    申请人： Michael P. Chudzik ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

    发明人： Michael P. Chudzik ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

    IPC分类号： H01L21/8238 ,  H01L29/49 ,  H01L29/51

    CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

    摘要： Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

    摘要翻译： 公开了使用具有高k /金属栅极叠层的封盖层的IC和相关晶体管。 在一个实施例中，IC包括具有包括第一金属，第二金属和第一介电层的栅电极的第一类型晶体管，第一介电层包括氧; 通过隔离区与第一型晶体管分离的第二类型晶体管，第二类型晶体管具有包括具有适合于第二类型晶体管和第一介电层的功函数的第二金属的栅电极; 并且其中所述第一类型晶体管的栅极包括在所述第一金属和所述第二金属之间的稀土金属，并且所述第二类型晶体管的栅电极包括由所述稀土金属的氧化物制成的第二电介质层。

    HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS
    4.
    发明申请
    HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS 有权
    使用覆盖层方法，IC和相关晶体管的高K /金属栅极堆叠

    公开(公告)号：US20120184093A1

    公开(公告)日：2012-07-19

    申请号：US13433659

    申请日：2012-03-29

    申请人： Michael P. Chudzik ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

    发明人： Michael P. Chudzik ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

    IPC分类号： H01L21/28

    CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

    摘要： Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

    摘要翻译： 公开了使用具有高k /金属栅极叠层的封盖层的IC和相关晶体管。 在一个实施例中，IC包括具有包括第一金属，第二金属和第一介电层的栅电极的第一类型晶体管，第一介电层包括氧; 通过隔离区与第一型晶体管分离的第二类型晶体管，第二类型晶体管具有包括具有适合于第二类型晶体管和第一介电层的功函数的第二金属的栅电极; 并且其中所述第一类型晶体管的栅极包括在所述第一金属和所述第二金属之间的稀土金属，并且所述第二类型晶体管的栅电极包括由所述稀土金属的氧化物制成的第二电介质层。

    HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS
    5.
    发明申请
    HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS 审中-公开
    使用覆盖层方法，IC和相关晶体管的高K /金属栅极堆叠

    公开(公告)号：US20090152636A1

    公开(公告)日：2009-06-18

    申请号：US11954749

    申请日：2007-12-12

    申请人： Michael P. Chudzik ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

    发明人： Michael P. Chudzik ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

    IPC分类号： H01L21/336 ,  H01L27/092 ,  H01L29/78

    CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

    摘要： Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

    摘要翻译： 公开了使用具有高k /金属栅极叠层的封盖层的IC和相关晶体管。 在一个实施例中，IC包括具有包括第一金属，第二金属和第一介电层的栅电极的第一类型晶体管，第一介电层包括氧; 通过隔离区与第一型晶体管分离的第二类型晶体管，第二类型晶体管具有包括具有适合于第二类型晶体管和第一介电层的功函数的第二金属的栅电极; 并且其中所述第一类型晶体管的栅极包括在所述第一金属和所述第二金属之间的稀土金属，并且所述第二类型晶体管的栅电极包括由所述稀土金属的氧化物制成的第二电介质层。

    Gate Effective-Workfunction Modification for CMOS
    6.
    发明申请
    Gate Effective-Workfunction Modification for CMOS 有权
    门有效功能修改CMOS

    公开(公告)号：US20110121401A1

    公开(公告)日：2011-05-26

    申请号：US13019949

    申请日：2011-02-02

    申请人： Dae-Gyu Park ,  Michael P. Chudzik ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Dae-Gyu Park ,  Michael P. Chudzik ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/785

    摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

    摘要翻译： 公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。 在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。 还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

    Gate effective-workfunction modification for CMOS
    7.
    发明授权
    Gate effective-workfunction modification for CMOS 有权
    CMOS有效功能修改功能

    公开(公告)号：US07947549B2

    公开(公告)日：2011-05-24

    申请号：US12037158

    申请日：2008-02-26

    申请人： Dae-Gyu Park ,  Michael P Chudzik ,  Rashmi Jha ,  Siddarth A Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Dae-Gyu Park ,  Michael P Chudzik ,  Rashmi Jha ,  Siddarth A Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/785

    摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

    摘要翻译： 公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。 在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。 还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

    Gate Effective-Workfunction Modification for CMOS
    8.
    发明申请
    Gate Effective-Workfunction Modification for CMOS 有权
    门有效功能修改CMOS

    公开(公告)号：US20090212369A1

    公开(公告)日：2009-08-27

    申请号：US12037158

    申请日：2008-02-26

    申请人： Dae-Gyu Park ,  Michael P. Chudzik ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Dae-Gyu Park ,  Michael P. Chudzik ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/785

    摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

    摘要翻译： 公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。 在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。 还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

    Gate effective-workfunction modification for CMOS
    9.
    发明授权
    Gate effective-workfunction modification for CMOS 有权
    CMOS有效功能修改功能

    公开(公告)号：US08183642B2

    公开(公告)日：2012-05-22

    申请号：US13019949

    申请日：2011-02-02

    申请人： Dae-Gyu Park ,  Michael P Chudzik ,  Rashmi Jha ,  Siddarth A Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Dae-Gyu Park ,  Michael P Chudzik ,  Rashmi Jha ,  Siddarth A Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/785

    摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

    摘要翻译： 公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。 在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。 还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。