公开(公告)号：US20080203485A1

公开(公告)日：2008-08-28

申请号：US11680108

申请日：2007-02-28

申请人： Michael P. Chudzik ,  Wei He ,  Renee T. Mo ,  Naim Moumen ,  Vijay Narayanan ,  Dae-gyu Park ,  Vamsi Paruchuri

发明人： Michael P. Chudzik ,  Wei He ,  Renee T. Mo ,  Naim Moumen ,  Vijay Narayanan ,  Dae-gyu Park ,  Vamsi Paruchuri

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78 ,  H01L29/7845

摘要： A gate structure for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack having a first gate dielectric layer formed over a substrate, and a first metal layer formed over the first gate dielectric layer. A second gate stack includes a second gate dielectric layer formed over the substrate and a second metal layer formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.

摘要翻译： 用于互补金属氧化物半导体（CMOS）器件的栅极结构包括具有形成在衬底上的第一栅极介电层的第一栅极堆叠和形成在第一栅极介电层上的第一金属层。 第二栅极堆叠包括形成在衬底上的第二栅极电介质层和形成在第二栅极介电层上的第二金属层。 第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

公开(公告)号：US07947549B2

公开(公告)日：2011-05-24

申请号：US12037158

申请日：2008-02-26

申请人： Dae-Gyu Park ,  Michael P Chudzik ,  Rashmi Jha ,  Siddarth A Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Dae-Gyu Park ,  Michael P Chudzik ,  Rashmi Jha ,  Siddarth A Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/785

摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

摘要翻译： 公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。 在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。 还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

公开(公告)号：US20110121401A1

公开(公告)日：2011-05-26

申请号：US13019949

申请日：2011-02-02

申请人： Dae-Gyu Park ,  Michael P. Chudzik ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Dae-Gyu Park ,  Michael P. Chudzik ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L27/092

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/785

摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

摘要翻译： 公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。 在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。 还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

公开(公告)号：US20090212369A1

公开(公告)日：2009-08-27

申请号：US12037158

申请日：2008-02-26

申请人： Dae-Gyu Park ,  Michael P. Chudzik ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Dae-Gyu Park ,  Michael P. Chudzik ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/785

摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

摘要翻译： 公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。 在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。 还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

公开(公告)号：US08183642B2

公开(公告)日：2012-05-22

申请号：US13019949

申请日：2011-02-02

申请人： Dae-Gyu Park ,  Michael P Chudzik ,  Rashmi Jha ,  Siddarth A Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Dae-Gyu Park ,  Michael P Chudzik ,  Rashmi Jha ,  Siddarth A Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/785

摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

摘要翻译： 公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。 在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。 还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

公开(公告)号：US08030716B2

公开(公告)日：2011-10-04

申请号：US12883874

申请日：2010-09-16

申请人： Dae-Gyu Park ,  Michael P. Chudzik ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Dae-Gyu Park ,  Michael P. Chudzik ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/70

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/785

摘要： A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.

摘要翻译： 公开了一种用于制造CMOS结构的方法。 该方法包括在NFET器件和PFET器件中的高k栅极绝缘体层的覆盖布置以及NFET器件上的栅极金属层的实现。 之后是在NFET器件和PFET器件上的Al层的覆盖布置。 该方法还包括在Al层上共享的栅极金属层的布置布置。 当PFET器件暴露于热退火时，高k电介质氧化Al层，从而将Al层转变为PFET界面控制层，而在NFET器件中，Al成为金属栅极的一个区域。

公开(公告)号：US20110001195A1

公开(公告)日：2011-01-06

申请号：US12883874

申请日：2010-09-16

申请人： Dae-Gyu Park ,  Michael P. Chudzik ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Dae-Gyu Park ,  Michael P. Chudzik ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/785

摘要： A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.

摘要翻译： 公开了一种用于制造CMOS结构的方法。 该方法包括在NFET器件和PFET器件中的高k栅极绝缘体层的覆盖布置以及NFET器件上的栅极金属层的实现。 之后是在NFET器件和PFET器件上的Al层的覆盖布置。 该方法还包括在Al层上共享的栅极金属层的布置布置。 当PFET器件暴露于热退火时，高k电介质氧化Al层，从而将Al层转变为PFET界面控制层，而在NFET器件中，Al成为金属栅极的一个区域。

公开(公告)号：US20090283838A1

公开(公告)日：2009-11-19

申请号：US12120658

申请日：2008-05-15

申请人： Dae-Gyu Park ,  Michael P. Chudzik ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Dae-Gyu Park ,  Michael P. Chudzik ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/785

摘要： A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.

摘要翻译： 公开了一种用于制造CMOS结构的方法。 该方法包括在NFET器件和PFET器件中的高k栅极绝缘体层的覆盖布置以及NFET器件上的栅极金属层的实现。 之后是在NFET器件和PFET器件上的Al层的覆盖布置。 该方法还包括在Al层上共享的栅极金属层的布置布置。 当PFET器件暴露于热退火时，高k电介质氧化Al层，从而将Al层转变为PFET界面控制层，而在NFET器件中，Al成为金属栅极的一个区域。

公开(公告)号：US07863126B2

公开(公告)日：2011-01-04

申请号：US12120658

申请日：2008-05-15

申请人： Dae-Gyu Park ,  Michael P. Chudzik ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Dae-Gyu Park ,  Michael P. Chudzik ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/441

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/785

摘要： A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.

摘要翻译： 公开了一种用于制造CMOS结构的方法。 该方法包括在NFET器件和PFET器件中的高k栅极绝缘体层的覆盖布置以及NFET器件上的栅极金属层的实现。 之后是在NFET器件和PFET器件上的Al层的覆盖布置。 该方法还包括在Al层上共享的栅极金属层的布置布置。 当PFET器件暴露于热退火时，高k电介质氧化Al层，从而将Al层转变为PFET界面控制层，而在NFET器件中，Al成为金属栅极的一个区域。

公开(公告)号：US07919379B2

公开(公告)日：2011-04-05

申请号：US11852906

申请日：2007-09-10

申请人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

发明人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

IPC分类号： H01L21/00 ,  H01L21/336

CPC分类号： H01L21/31116 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

摘要翻译： 本发明涉及半导体器件，更具体地说，涉及一种基本上不去除半导体衬底去除对半导体衬底的表面有选择性的介电隔离层的工艺和结构。 本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。 该方法包括在半导体衬底上形成场效应晶体管，所述FET包括电介质间隔物和所述栅极结构，所述电介质隔离物邻近所述栅极结构的侧壁并位于所述半导体衬底中的源极/漏极区域上; 在FET上沉积第一氮化物层; 并且基本上不去除半导体衬底，去除对半导体衬底的选择性的氮化物层和电介质衬垫。