公开(公告)号：US20100041221A1

公开(公告)日：2010-02-18

申请号：US12541562

申请日：2009-08-14

申请人： John C. Arnold ,  Glenn A. Biery ,  Alessandro C. Callegari ,  Tze-Chiang Chen ,  Michael P. Chudzik ,  Bruce B. Doris ,  Michael A. Gribelyuk ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Joseph S. Newbury ,  Vamsi K. Paruchuri ,  Michelle L. Steen

发明人： John C. Arnold ,  Glenn A. Biery ,  Alessandro C. Callegari ,  Tze-Chiang Chen ,  Michael P. Chudzik ,  Bruce B. Doris ,  Michael A. Gribelyuk ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Joseph S. Newbury ,  Vamsi K. Paruchuri ,  Michelle L. Steen

IPC分类号： H01L21/28

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.

摘要翻译： 本发明涉及互补金属氧化物半导体（CMOS）电路，其各自包含至少第一和第二栅极堆叠。 第一栅极堆叠位于半导体衬底中的第一器件区域（例如，n-FET器件区域）上，并且至少从底部至顶部包括栅极介电层，金属栅极导体和含硅的 门导体。 第二栅极堆叠位于半导体衬底中的第二器件区域（例如，p-FET器件区域）上，并且至少包括从栅极电介质层和含硅栅极导体的底部到顶部。 可以通过本发明的各种方法以集成的方式在半导体衬底上形成第一和第二栅极叠层。

公开(公告)号：US20090283830A1

公开(公告)日：2009-11-19

申请号：US12508177

申请日：2009-07-23

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen

IPC分类号： H01L27/12 ,  H01L27/092

CPC分类号： H01L21/823842

摘要： A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.

摘要翻译： 包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，其分别包括具有nFET行为的金属栅极和pFET行为，而不包括上多晶硅栅极 提供电极。 本发明还提供一种制造这种半导体结构的方法。

公开(公告)号：US20080308872A1

公开(公告)日：2008-12-18

申请号：US11763047

申请日：2007-06-14

申请人： Huiming Bu ,  Eduard A. Cartier ,  Bruce B. Doris ,  Young-Hee Kim ,  Barry Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen

发明人： Huiming Bu ,  Eduard A. Cartier ,  Bruce B. Doris ,  Young-Hee Kim ,  Barry Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.

摘要翻译： 在半导体衬底上形成包含第一高k电介质部分的NFET和包含第二高k栅极电介质部分的PFET。 栅极侧壁氮化物形成在NFET的栅极上，而PFET的侧壁保持没有栅极侧壁氮化物。 直接在PFET栅极堆叠的侧壁上和NFET上的栅极侧壁氮化物上形成氧化物间隔物。 在高温处理之后，第一和第二介质部分含有非化学计量的缺氧高k电介质材料。 半导体结构在氧气环境中进行退火，在该环境中，氧气通过氧化物间隔物扩散到第二高k电介质部分。 PFET包括更高化学计量的高k电介质材料，并且NFET包含较少化学计量的高k电介质材料。 本发明优化了PFET和NFET的阈值电压。

公开(公告)号：US08035173B2

公开(公告)日：2011-10-11

申请号：US12712371

申请日：2010-02-25

申请人： Huiming Bu ,  Eduard A. Cartier ,  Bruce B. Doris ,  Young-Hee Kim ,  Barry Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen

发明人： Huiming Bu ,  Eduard A. Cartier ,  Bruce B. Doris ,  Young-Hee Kim ,  Barry Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen

IPC分类号： H01L29/78

CPC分类号： H01L21/823864 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.

摘要翻译： 在半导体衬底上形成包含第一高k电介质部分的NFET和包含第二高k栅极电介质部分的PFET。 栅极侧壁氮化物形成在NFET的栅极上，而PFET的侧壁保持没有栅极侧壁氮化物。 直接在PFET栅极堆叠的侧壁上和NFET上的栅极侧壁氮化物上形成氧化物间隔物。 在高温处理之后，第一和第二介质部分含有非化学计量的缺氧高k电介质材料。 半导体结构在氧气环境中进行退火，在该环境中，氧气通过氧化物间隔物扩散到第二高k电介质部分。 PFET包括更高化学计量的高k电介质材料，并且NFET包含较少化学计量的高k电介质材料。 本发明优化了PFET和NFET的阈值电压。

公开(公告)号：US20090298244A1

公开(公告)日：2009-12-03

申请号：US12537275

申请日：2009-08-07

申请人： Bruce B. Doris ,  Cyril Cabral, JR. ,  Elizabeth A. Duch ,  Stephen M. Rossnagel ,  Michelle L. Steen

发明人： Bruce B. Doris ,  Cyril Cabral, JR. ,  Elizabeth A. Duch ,  Stephen M. Rossnagel ,  Michelle L. Steen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L29/4958 ,  H01L29/7845

摘要： NFET and PFET devices with separately stressed channel regions, and methods of their fabrication is disclosed. A FET is disclosed which includes a gate, which gate includes a metal in a first state of stress. The FET also includes a channel region hosted in a single crystal Si based material, which channel region is overlaid by the gate and is in a second state of stress. The second state of stress of the channel region is of an opposite sign than the first state of stress of the metal included in the gate. The NFET channel is usually in a tensile state of stress, while the PFET channel is usually in a compressive state of stress. The methods of fabrication include the deposition of metal layers by physical vapor deposition (PVD), in such manner that the layers are in stressed states.

摘要翻译： 具有单独应力通道区域的NFET和PFET器件及其制造方法。 公开了一种FET，其包括栅极，该栅极包括处于第一应力状态的金属。 FET还包括托管在单晶Si基材料中的沟道区域，该沟道区域被栅极覆盖并处于第二应力状态。 沟道区域的第二应力状态与包括在栅极中的金属的第一应力状态相反。 NFET通道通常处于应力的拉伸状态，而PFET通道通常处于应力的压缩状态。 制造方法包括通过物理气相沉积（PVD）沉积金属层，使得层处于应力状态。

公开(公告)号：US07473975B2

公开(公告)日：2009-01-06

申请号：US11840774

申请日：2007-08-17

申请人： Glenn A. Biery ,  Ghavam Shahidi ,  Michelle L. Steen

发明人： Glenn A. Biery ,  Ghavam Shahidi ,  Michelle L. Steen

IPC分类号： H01L29/76

CPC分类号： H01L29/6656 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/51 ,  H01L29/66545

摘要： A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of the source/drain surface metal silicide layers and before formation of the silicided metal gate, in order to prevent formation of additional metal silicide structures in the source/drain regions during the gate salicidation process. The resulting semiconductor device structure includes a fully silicide metal gate that either comprises a different metal silicide material from that in the source/drain surface metal silicide layers, or has a thickness that is larger than that of the source/drain surface metal silicide layers. The source/drain regions of the semiconductor device structure are devoid of other metal silicide structures besides the surface metal silicide layers.

摘要翻译： 一种形成半导体器件结构的方法，包括以下步骤：在多晶硅栅叠层中独立地形成源极/漏极表面金属硅化物层和完全硅化金属栅极。 具体地说，在形成源极/漏极表面金属硅化物层之后并且在形成硅化金属栅极之前，在多晶硅栅极堆叠的侧壁上提供一组或多组间隔结构，以防止在其中形成附加的金属硅化物结构 源极/漏极区域在栅极盐化过程中。 所得到的半导体器件结构包括完全硅化物金属栅极，该栅极或者包含与源/漏表面金属硅化物层中的不同的金属硅化物材料，或者具有比源极/漏极表面金属硅化物层的厚度更大的厚度。 除了表面金属硅化物层之外，半导体器件结构的源极/漏极区域没有其它金属硅化物结构。

公开(公告)号：US06815813B1

公开(公告)日：2004-11-09

申请号：US10604211

申请日：2003-07-01

申请人： Timothy J. Dalton ,  Kevin S. Petrarca ,  Michelle L. Steen ,  Cornelia K. Tsang ,  Richard P. Volant

发明人： Timothy J. Dalton ,  Kevin S. Petrarca ,  Michelle L. Steen ,  Cornelia K. Tsang ,  Richard P. Volant

IPC分类号： H01L2334

CPC分类号： H01L23/58 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method are provided for thermal dissipation from a heat producing electronic device. The system includes a substrate for fabricating integrated circuits, the substrate having a first face and a second face. The second face is disposed substantially parallel to the first face having an electronic device disposed therein. A metallized crack stop is disposed in the first face surrounding the electronic device. A plurality of first metal conduits extend through the substrate from the second face thereof to the crack stop, wherein each first metal conduit is in thermal contact with the crack stop to provide a thermal drain from the electronic device to the second face.

摘要翻译： 提供了一种从制热电子设备散热的系统和方法。 该系统包括用于制造集成电路的基板，该基板具有第一面和第二面。 第二面基本上平行于第一面设置，其中设置有电子装置。 在电子设备周围的第一面设有金属化的裂纹停止件。 多个第一金属导管从其第二面延伸穿过基板到裂缝停止部，其中每个第一金属导管与裂纹停止件热接触以提供从电子装置到第二面的热耗散。

公开(公告)号：US08080876B2

公开(公告)日：2011-12-20

申请号：US12147466

申请日：2008-06-26

申请人： Paul S. Andry ,  John U. Knickerbocker ,  Michelle L. Steen ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John U. Knickerbocker ,  Michelle L. Steen ,  Cornelia K. Tsang

IPC分类号： H01L23/538

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.

摘要翻译： 一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。 与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。 通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。

公开(公告)号：US07872317B2

公开(公告)日：2011-01-18

申请号：US12508177

申请日：2009-07-23

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen

IPC分类号： H01L21/70

CPC分类号： H01L21/823842

摘要： A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.

摘要翻译： 包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，其分别包括具有nFET行为的金属栅极和pFET行为，而不包括上多晶硅栅极 提供电极。 本发明还提供一种制造这种半导体结构的方法。

公开(公告)号：US07785999B2

公开(公告)日：2010-08-31

申请号：US11830277

申请日：2007-07-30

申请人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

发明人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

IPC分类号： H01L21/44 ,  H01L21/8242

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L21/823443 ,  H01L29/66545

摘要： An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

摘要翻译： 提供了一种先进的栅极结构，其包括完全硅化金属栅极和硅化物源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。