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1.发明授权Apparatus and method for performing a defect leakage screen test for memory devices 失效用于对存储器件执行缺陷泄漏屏测试的装置和方法公开(公告)号：US06330697B1
公开(公告)日：2001-12-11
申请号：US09294866
申请日：1999-04-20
IPC分类号： G11C2900
CPC分类号： G11C29/025 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50 , G11C2029/5004 , G11C2029/5006
摘要： A Defect Leakage Screen Test apparatus and method is introduced to eliminate or reduce steps in the failure analysis process of memory devices, such as DRAM cells, or to eliminate the necessity for the application of a physical failure analysis on the memory device. Special single bit failures due to leakage current, junction current, or threshold leakage current, are characterized by varying the p-well voltage of the memory device during the read operation of the test. The p-well voltage is varied with a test code Initial Program Load (IPL). Additional logic is provided on the memory IC to decode the IPL logic signals. In order to perform the p-well varying test, the memory device is provided with the following: IPL decoding logic; a reference voltage generator; an IPL voltage reference multiplexor; a p-well voltage feed-back circuit; and a differential amplifier circuit.
摘要翻译： 缺陷泄漏屏幕引入了测试设备和方法来消除或减少诸如DRAM单元之类的存储器件的故障分析过程中的步骤，或消除在存储器件上应用物理故障分析的必要性。特殊单位 由漏电流，结电流或阈值漏电流引起的故障的特征在于，在测试的读取操作期间改变存储器件的p阱电压.P阱电压随测试代码初始程序负载 IPL）。 在存储器IC上提供附加逻辑以对IPL逻辑信号进行解码。为了执行p阱变化测试，存储器件具有以下内容：IPL解码逻辑; 参考电压发生器; IPL电压参考多路复用器; p阱电压反馈电路; 和差分放大电路。
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2.发明申请POWER CONTROLLER, A METHOD OF OPERATING THE POWER CONTROLLER AND A SEMICONDUCTOR MEMORY SYSTEM EMPLOYING THE SAME 有权功率控制器，操作功率控制器的方法和使用其的半导体存储器系统公开(公告)号：US20080098244A1
公开(公告)日：2008-04-24
申请号：US11876600
申请日：2007-10-22
IPC分类号： G06F1/32
CPC分类号： G11C5/147
摘要： Embodiments of the present disclosure provide a power controller, a method of operating a power controller and a semiconductor memory system. In one embodiment, the power controller is for use with a memory and includes an access module configured to provide an active state of the memory to allow memory access. The power controller also includes a retain-till-access module configured to cycle a portion of the memory between the active state and a low leakage data retention state of the memory. The power controller further includes an expanded retain-till-access module configured to extend the active state of the memory for a specified period of time before returning the memory to the low leakage data retention state.
摘要翻译： 本公开的实施例提供了功率控制器，操作功率控制器和半导体存储器系统的方法。 在一个实施例中，功率控制器用于存储器并且包括被配置为提供存储器的活动状态以允许存储器访问的访问模块。 功率控制器还包括保留直到访问模块，其被配置为在存储器的活动状态和低泄漏数据保持状态之间循环存储器的一部分。 功率控制器还包括扩展的保留直到访问模块，其被配置为在将存储器返回到低泄漏数据保持状态之前将存储器的活动状态延长指定的时间段。
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3.发明授权Memory device having asymmetrical CAS to data input/output mapping and applications thereof 失效具有不对称CAS到数据输入/输出映射的存储器件及其应用
公开(公告)号：US5412613A
公开(公告)日：1995-05-02
申请号：US161279
申请日：1993-12-06
IPC分类号： G06F12/02 , G11C5/00 , G11C7/10 , G11C7/22 , G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C7/22 , G11C7/1006
摘要： A semiconductor memory chip architecture is described implementing of a multi-bit data control function which enables independent control of at least a plurality of data bits via a single control signal. A logically organized memory chip is organized as a 2.sup.n x 4 chip in which one control (CAS0) signal enables a single data bit and another control (CAS1) signal enables the remaining three data bits. By organizing data control on chips in this manner, it becomes possible to optimize design modules such that a minimum number of control signals are used.
摘要翻译： 描述了实现多位数据控制功能的半导体存储器芯片架构，其通过单个控制信号独立地控制至少多个数据位。 逻辑组织的存储器芯片被组织为2nx 4芯片，其中一个控制（CAS0）信号使能单个数据位，另一个控制（CAS1）信号使能剩余的三个数据位。 通过以这种方式组织芯片上的数据控制，可以优化设计模块，使得使用最少数量的控制信号。
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公开(公告)号：US08756558B2
公开(公告)日：2014-06-17
申请号：US13435718
申请日：2012-03-30
申请人： David J. Toops , Michael P. Clinton
发明人： David J. Toops , Michael P. Clinton
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A computer program for generating a layout for a ferroelectric random access memory (FRAM) that is embodied on a non-transitory storage medium and executable by a processor is provided. FRAM specifications are received, and an FRAM floorplan and design rules are retrieved from the non-transitory storage medium. The layout for the FRAM based on the FRAM specifications and design rules is then assembled.
摘要翻译： 提供一种用于生成体现在非暂时性存储介质上并由处理器执行的铁电随机存取存储器（FRAM）的布局的计算机程序。 接收到FRAM规范，并从非暂时性存储介质中检索FRAM平面图和设计规则。 然后组装基于FRAM规范和设计规则的FRAM布局。
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公开(公告)号：US20130258751A1
公开(公告)日：2013-10-03
申请号：US13435718
申请日：2012-03-30
申请人： David J. Toops , Michael P. Clinton
发明人： David J. Toops , Michael P. Clinton
CPC分类号： G06F17/5068
摘要： A computer program for generating a layout for a ferroelectric random access memory (FRAM) that is embodied on a non-transitory storage medium and executable by a processor is provided. FRAM specifications are received, and an FRAM floorplan and design rules are retrieved from the non-transitory storage medium. The layout for the FRAM based on the FRAM specifications and design rules is then assembled.
摘要翻译： 提供一种用于生成体现在非暂时性存储介质上并由处理器执行的铁电随机存取存储器（FRAM）的布局的计算机程序。 接收到FRAM规范，并从非暂时性存储介质中检索FRAM平面图和设计规则。 然后组装基于FRAM规范和设计规则的FRAM布局。
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公开(公告)号：US5969997A
公开(公告)日：1999-10-19
申请号：US942825
申请日：1997-10-02
IPC分类号： G11C11/41 , G11C11/401 , G11C11/407 , G11C11/409 , G11C15/00
CPC分类号： G11C11/409 , G11C11/407
摘要： A high speed Random Access Memory (RAM) array device includes several logical banks, each of which can be uniquely addressed. Each of these logical banks contains a unique memory array segment and associated page register, the latter serving as a temporary storage location during high-speed page hit operations. To reduce latency during an initial page hit, further array optimization is realized by segmenting each logical bank into two segments with one, smaller segment, comprising a faster random access memory (FRAM) for storing initial data in a data stream. A high speed page register connects the FRAM directly to a multiplexer/demultiplexer connected to the device I/O ports bypassing an internal bus protocol such that the initial data can be transferred between the FRAM and the I/O ports faster thereby improving page-hit latency. Hence, segmenting the logical banks to include only a small high speed segment results in a performance gain approaching what could be achieved by implementing the entire memory device with a high speed FRAM, but at much lower cost.
摘要翻译： 高速随机存取存储器（RAM）阵列器件包括几个逻辑存储体，每个逻辑存储体可以被唯一地寻址。 这些逻辑组中的每一个包含唯一的存储器阵列段和相关联的页寄存器，后者在高速页命中操作期间用作临时存储位置。 为了在初始页面命中期间减少延迟，通过将每个逻辑存储体分割成具有一个较小段的两个段来实现进一步的阵列优化，其包括用于在数据流中存储初始数据的更快的随机存取存储器（FRAM）。 高速页寄存器将FRAM直接连接到绕过内部总线协议的设备I / O端口连接的多路复用器/解复用器，从而可以更快地在FRAM和I / O端口之间传输初始数据，从而提高页命中率 潜伏。 因此，将逻辑存储体分割为仅包含小的高速段导致通过以高速FRAM实现整个存储器件而可以以低得多的成本实现可达到的性能增益。
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7.发明授权Power controller, a method of operating the power controller and a semiconductor memory system employing the same 有权功率控制器，操作功率控制器的方法和采用该功率控制器的半导体存储器系统公开(公告)号：US08266464B2
公开(公告)日：2012-09-11
申请号：US11876600
申请日：2007-10-22
IPC分类号： G06F1/32
CPC分类号： G11C5/147
摘要： Embodiments of the present disclosure provide a power controller, a method of operating a power controller and a semiconductor memory system. In one embodiment, the power controller is for use with a memory and includes an access module configured to provide an active state of the memory to allow memory access. The power controller also includes a retain-till-access module configured to cycle a portion of the memory between the active state and a low leakage data retention state of the memory. The power controller further includes an expanded retain-till-access module configured to extend the active state of the memory for a specified period of time before returning the memory to the low leakage data retention state.
摘要翻译： 本公开的实施例提供了功率控制器，操作功率控制器和半导体存储器系统的方法。 在一个实施例中，功率控制器用于存储器并且包括被配置为提供存储器的活动状态以允许存储器访问的访问模块。 功率控制器还包括保留直到访问模块，其被配置为在存储器的活动状态和低泄漏数据保持状态之间循环存储器的一部分。 功率控制器还包括扩展的保留直到访问模块，其被配置为在将存储器返回到低泄漏数据保持状态之前将存储器的活动状态延长指定的时间段。
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8.发明授权Tunable voltage controller for a sub-circuit and method of operating the same 有权用于子电路的可调电压控制器及其操作方法公开(公告)号：US07671663B2
公开(公告)日：2010-03-02
申请号：US11609678
申请日：2006-12-12
IPC分类号： H03K3/01
CPC分类号： G05F3/205
摘要： The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.
摘要翻译： 本发明提供一种与子电路一起使用的可调电压控制器。 在一个实施例中，可调谐电压控制器包括二极管连接的MOS晶体管，其包含在衬底的掺杂阱中并被配置为提供用于子电路的电压。 此外，可调谐电压控制器还包括偏置单元，其被配置为通过将掺杂阱选择性地连接到多个电压源中的一个或可变电压源来调节电压。
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9.发明申请TUNABLE VOLTAGE CONTROLLER FOR A SUB-CIRCUIT AND METHOD OF OPERATING THE SAME 有权用于子电路的可控电压控制器及其操作方法公开(公告)号：US20080136497A1
公开(公告)日：2008-06-12
申请号：US11609678
申请日：2006-12-12
IPC分类号： G05F1/10
CPC分类号： G05F3/205
摘要： The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.
摘要翻译： 本发明提供一种与子电路一起使用的可调电压控制器。 在一个实施例中，可调谐电压控制器包括二极管连接的MOS晶体管，其包含在衬底的掺杂阱中并被配置为提供用于子电路的电压。 此外，可调谐电压控制器还包括偏置单元，其被配置为通过将掺杂阱选择性地连接到多个电压源中的一个或可变电压源来调节电压。
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