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公开(公告)号：US5969997A
公开(公告)日：1999-10-19
申请号：US942825
申请日：1997-10-02
IPC分类号： G11C11/41 , G11C11/401 , G11C11/407 , G11C11/409 , G11C15/00
CPC分类号： G11C11/409 , G11C11/407
摘要： A high speed Random Access Memory (RAM) array device includes several logical banks, each of which can be uniquely addressed. Each of these logical banks contains a unique memory array segment and associated page register, the latter serving as a temporary storage location during high-speed page hit operations. To reduce latency during an initial page hit, further array optimization is realized by segmenting each logical bank into two segments with one, smaller segment, comprising a faster random access memory (FRAM) for storing initial data in a data stream. A high speed page register connects the FRAM directly to a multiplexer/demultiplexer connected to the device I/O ports bypassing an internal bus protocol such that the initial data can be transferred between the FRAM and the I/O ports faster thereby improving page-hit latency. Hence, segmenting the logical banks to include only a small high speed segment results in a performance gain approaching what could be achieved by implementing the entire memory device with a high speed FRAM, but at much lower cost.
摘要翻译： 高速随机存取存储器（RAM）阵列器件包括几个逻辑存储体，每个逻辑存储体可以被唯一地寻址。 这些逻辑组中的每一个包含唯一的存储器阵列段和相关联的页寄存器，后者在高速页命中操作期间用作临时存储位置。 为了在初始页面命中期间减少延迟，通过将每个逻辑存储体分割成具有一个较小段的两个段来实现进一步的阵列优化，其包括用于在数据流中存储初始数据的更快的随机存取存储器（FRAM）。 高速页寄存器将FRAM直接连接到绕过内部总线协议的设备I / O端口连接的多路复用器/解复用器，从而可以更快地在FRAM和I / O端口之间传输初始数据，从而提高页命中率 潜伏。 因此，将逻辑存储体分割为仅包含小的高速段导致通过以高速FRAM实现整个存储器件而可以以低得多的成本实现可达到的性能增益。
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公开(公告)号：US6070262A
公开(公告)日：2000-05-30
申请号：US833367
申请日：1997-04-04
CPC分类号： G11C7/1057 , G06F11/1044 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A Dynamic Random Access Memory (DRAM) configurable by eight (.times.8) or by nine (.times.9). The DRAM has nine Data Input/Outputs (I/Os). The memory array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is configured .times.8, one I/O is held in its high impedance state; one ninth of the DRAM's data path (between the array and the ninth I/O) is ignored; and, the entire array address space is available for data storage through eight I/Os. When the DRAM is configured .times.9, all nine I/Os are active; the DRAM I/O path is reconfigured with part of the array providing the ninth bit through the ninth I/O; and the array address space reduced by one-eighth. All nine bits may be from a common sub-array. Alternatively, sub-arrays may be paired so that when the DRAM is configured .times.9, eight bits are accessed in seven-eighths of one sub-array, with the ninth bit being accessed in one eighth of the other sub-array of the pair.
摘要翻译： 动态随机存取存储器（DRAM）可由八（x8）或九（x9）配置。 DRAM具有9个数据输入/输出（I / O）。 存储器阵列被分成两个或更多个子阵列，子阵列单元被布置成可寻址的行和列。 当DRAM被配置为x8时，一个I / O保持在其高阻抗状态; DRAM的数据路径（阵列和第九个I / O之间）的九分之一被忽略; 并且整个阵列地址空间可用于通过八个I / O进行数据存储。 当DRAM配置为x9时，所有9个I / O都有效; DRAM I / O路径被配置为通过第九个I / O提供第九位的阵列的一部分; 并且阵列地址空间减少了八分之一。 所有9位可能来自公共子阵列。 或者，子阵列可以配对，使得当DRAM被配置为x9时，在一个子阵列的七分之八中访问八个比特，其中第九比特在该对的另一个子阵列的八分之一中被访问。
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公开(公告)号：US6065093A
公开(公告)日：2000-05-16
申请号：US79572
申请日：1998-05-15
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G06F13/00
CPC分类号： G11C7/1072 , G11C7/22
摘要： A memory device is provided which stacks commands and internally executes each command at the appropriate time, thereby ensuring contiguous data I/O. The memory device is capable of initiating memory accesses either immediately or "stacking" the command along with a "clock count". The clock count defines the number of clock cycles that must occur prior to execution of the command by the memory device. The memory device initiates memory accesses either immediately, or delayed by the number of clocks defined by the clock count for that command. The memory device operates as a slave to the memory controller and therefore has no ability to execute instructions at a time other than that defined by the memory controller.
摘要翻译： 提供一种存储器件，其堆叠命令并在适当的时间内部执行每个命令，从而确保连续的数据I / O。 存储器件能够立即启动存储器访问或者“堆叠”命令以及“时钟计数”。 时钟计数定义在存储器件执行命令之前必须发生的时钟周期数。 存储器设备立即启动存储器访问，或延迟由该命令的时钟计数定义的时钟数。 存储器件作为存储器控制器的从设备操作，因此在与由存储器控制器定义的时间以外的时间不具有执行指令的能力。
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公开(公告)号：US06178517B1
公开(公告)日：2001-01-23
申请号：US09121933
申请日：1998-07-24
IPC分类号： G06F1200
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.
摘要翻译： 高带宽DRAM具有将DRAM连接到处理器的两个单独的总线网络。 一个总线网络是高速（例如，500MHz）8：1或16：1多路复用I / O总线，第二个是较慢（例如，64位）总线。 例如，高速总线用于需要快速访问DRAM存储器阵列中大量位的图形密集型应用。 这当然会导致更高的功率需求。 由于并非所有应用都需要在DRAM和处理器之间传输大量数据，所以为这些不太要求苛刻的应用程序提供较慢的总线，例如文字处理器，电子表格等。 较慢的总线需要更少的功率来进行操作，因此导致省电模式，其中尤其有助于延长电池寿命。
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公开(公告)号：US5896404A
公开(公告)日：1999-04-20
申请号：US833371
申请日：1997-04-04
CPC分类号： G06F11/1008 , G11C7/1018 , G06F11/1052
摘要： A Dynamic Random Access Memory (DRAM) with a burst length programmable as eight (8) or nine (9) bytes. The DRAM array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is programmed in Normal mode, the burst length is 8 and the entire array address space is available for data storage. When the DRAM is programmed for error checking (ECC mode), the burst length is nine and the array is reconfigured with part of the array providing the ninth byte. The DRAM's address space is reduced by one-eighth in ECC mode. Preferably, all nine locations are in the same page, with each page being divided into eight equal portions. In Normal mode all eight equal portions are data storage; and, in ECC mode, seven-eighths of the page is data storage, the remaining one eighth being assigned to check bit storage.
摘要翻译： 具有可编程为八（8）或九（9）字节的突发长度的动态随机存取存储器（DRAM）。 DRAM阵列分为两个或更多个子阵列，子阵列单元以可寻址的行和列排列。 当DRAM在正常模式下编程时，突发长度为8，整个阵列地址空间可用于数据存储。 当DRAM被编程用于错误检查（ECC模式）时，突发长度为9，并且阵列被配置为提供第九个字节的阵列的一部分。 在ECC模式下，DRAM的地址空间减少了八分之一。 优选地，所有九个位置在同一页面中，每个页面被分成八个相等的部分。 在正常模式下，所有八个相等的部分都是数据存储; 并且在ECC模式中，页面的七分之一是数据存储，剩下的八分之一被分配给校验位存储。
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6.发明授权Method and system for reducing an amount of power utilized by selecting a lowest power mode from a plurality of power modes 失效用于通过从多个功率模式中选择最低功率模式来减少所使用功率量的方法和系统
公开(公告)号：US5404543A
公开(公告)日：1995-04-04
申请号：US891367
申请日：1992-05-29
IPC分类号： G06F1/26 , G06F1/32 , G06F12/06 , G11C11/406
CPC分类号： G06F1/3215 , G06F1/3275 , Y02B60/1225 , Y02B60/1228
摘要： A method and system for managing the utilization of power is provided. In a system having one or more devices, such as a memory subsystem having one or more banks of memory, the amount of power necessary for the operation of one or more of the devices is monitored and if possible, the power being supplied to one or more of the devices is reduced. A scoreboard located within a memory controller is used to retain the available power modes for each of the devices. When it is determined that it is desirable to reduce the power being supplied to a particular device, then the scoreboard is accessed in order to determine the lowest power level available for the device. Using this information, an amount of power commensurate with the lowest power level is applied to the device, thereby reducing the amount of power being applied to the device. In one aspect of the invention, a device is automatically placed in its lowest power level when it has not been accessed for a preselected amount of time.
摘要翻译： 提供了一种用于管理电力利用的方法和系统。 在具有一个或多个设备（例如具有一个或多个存储器存储器的存储器子系统）的系统中，监视用于一个或多个设备的操作所需的功率量，并且如果可能，将电力供应给一个或多个 更多的设备被减少。 位于存储器控制器内的记分板用于保持每个设备的可用功率模式。 当确定希望减少被提供给特定设备的功率时，则记录板被访问以便确定可用于该设备的最低功率级别。 使用该信息，将与功率水平相当的功率量施加到设备，从而减少施加到设备的功率量。 在本发明的一个方面，当设备在预选的时间量未被访问时，被自动地置于其最低功率水平。
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7.发明授权Memory device having asymmetrical CAS to data input/output mapping and applications thereof 失效具有不对称CAS到数据输入/输出映射的存储器件及其应用
公开(公告)号：US5412613A
公开(公告)日：1995-05-02
申请号：US161279
申请日：1993-12-06
IPC分类号： G06F12/02 , G11C5/00 , G11C7/10 , G11C7/22 , G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C7/22 , G11C7/1006
摘要： A semiconductor memory chip architecture is described implementing of a multi-bit data control function which enables independent control of at least a plurality of data bits via a single control signal. A logically organized memory chip is organized as a 2.sup.n x 4 chip in which one control (CAS0) signal enables a single data bit and another control (CAS1) signal enables the remaining three data bits. By organizing data control on chips in this manner, it becomes possible to optimize design modules such that a minimum number of control signals are used.
摘要翻译： 描述了实现多位数据控制功能的半导体存储器芯片架构，其通过单个控制信号独立地控制至少多个数据位。 逻辑组织的存储器芯片被组织为2nx 4芯片，其中一个控制（CAS0）信号使能单个数据位，另一个控制（CAS1）信号使能剩余的三个数据位。 通过以这种方式组织芯片上的数据控制，可以优化设计模块，使得使用最少数量的控制信号。
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公开(公告)号：US07646649B2
公开(公告)日：2010-01-12
申请号：US10707053
申请日：2003-11-18
IPC分类号： G11C11/00
CPC分类号： G06F13/4243 , G11C7/1078 , G11C7/109
摘要： A memory system having a plurality of DRAMs which are selectively provided non-inverted or inverted signals. The DRAMs have the ability to accept non-inverted or inverted address/command signals from a register that drives a plurality of signals simultaneously. The system includes DRAM receivers with programmable input polarity and a register with programmable output polarity.
摘要翻译： 具有选择性地提供非反相或反相信号的多个DRAM的存储器系统。 DRAM具有从同时驱动多个信号的寄存器接受非反相或反相地址/命令信号的能力。 该系统包括具有可编程输入极性的DRAM接收器和具有可编程输出极性的寄存器。
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公开(公告)号：US07480774B2
公开(公告)日：2009-01-20
申请号：US10249331
申请日：2003-04-01
IPC分类号： G06F12/00
CPC分类号： G11C7/109 , G06F11/1016 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C11/4076 , G11C11/408 , G11C11/4093 , G11C2207/104
摘要： A method for performing a common cancel (CC) function on a dynamic random access memory (DRAM) semiconductor device to improve reliability and speed of a memory system. The CC function rakes advantage of the intrinsic delays associated wit memory read operations at high clock frequencies, and the increased write latency commensurate with increased read latencies where non-zero larencies for read and write operations are the norm by permitting address and command ECC structures to operate in parallel with the address and command re-drive circuitt The CC function is extendable to future DDR2 and DDR3 operating requirements in which latency of higher frequency modes will increase due to the shift from 2 bit pre-fetch to 4 and 8 bit pre-fetch architecture.
摘要翻译： 一种用于在动态随机存取存储器（DRAM）半导体器件上执行公共取消（CC）功能以提高存储器系统的可靠性和速度的方法。 CC功能利用与高时钟频率下的存储器读取操作相关联的固有延迟的优点，以及与增加的读取延迟相对应的增加的写入延迟，其中用于读取和写入操作的非零光标是通过允许地址和命令ECC结构到 与地址和命令重新驱动电路并行操作CC功能可扩展到未来的DDR2和DDR3操作要求，其中由于从2位预取到4位和8位预取的更高频率模式的延迟将增加， 获取架构。
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10.发明授权Synchronous dynamic random access memory device having memory command cancel function 有权具有存储器命令取消功能的同步动态随机存取存储器件公开(公告)号：US06826113B2
公开(公告)日：2004-11-30
申请号：US10249273
申请日：2003-03-27
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： A synchronous dynamic random access memory (SDRAM) semiconductor device which uses a command cancel function to improve reliability and speed of a memory system. The CC function takes advantage of the intrinsic delays associated with memory read operations at high clock frequencies, and the increased write latency commensurate with increased read latencies where non-zero latencies for read and write operations are the norm by permitting address and command ECC structures to operate in parallel with the address and command re-drive circuits. The CC function is extendable to future DDR2 and DDR3 operating requirements in which latency of higher frequency modes will increase due to a shift from 2 bit pre-fetch to 4 and 8 bit pre-fetch architecture.
摘要翻译： 使用命令取消功能的同步动态随机存取存储器（SDRAM）半导体器件来提高存储器系统的可靠性和速度。 CC功能利用在高时钟频率下与存储器读取操作相关联的固有延迟，并且增加的写延迟与增加的读延迟相对应，其中用于读和写操作的非零延迟是通过允许地址和命令ECC结构到 与地址和命令重新驱动电路并行操作。 CC功能可扩展到未来的DDR2和DDR3操作要求，其中由于从2位预取到4和8位预取架构的转变，较高频率模式的延迟将增加。
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