Display processor and method for display processing

    公开(公告)号:US10109260B2

    公开(公告)日:2018-10-23

    申请号:US14766986

    申请日:2013-02-12

    IPC分类号: G09G5/397 G09G5/14 G06T11/60

    摘要: A display processor device is for processing display image data by overlaying a multitude of image layers. Pixel values of at least one of the image layers are stored in a memory and may comprise pixels values having a single predefined value, such as transparency. The display processor has a fetch unit for selectively fetching stored pixel values from the memory by skipping stored pixels values having the single predefined value according to a fetch mask indicative of pixels values having the single predetermined value. Advantageously the bandwidth for accessing the memory is reduced, because less pixel data values need be retrieved. Power consumption may be reduced, and slower memories may be applied.

    Display controller with blending stage
    3.
    发明授权
    Display controller with blending stage 有权
    显示控制器配合舞台

    公开(公告)号:US09483856B2

    公开(公告)日:2016-11-01

    申请号:US14394682

    申请日:2012-04-20

    摘要: A display controller comprising a blending stage and a blending controller. The blending stage is provided for blending multiple image layers into one display output image and comprises a plurality of input channels for receiving pixel data for the multiple image layers. The blending stage further comprises multiple blenders for combining the pixel data received by at least two input channels of the plurality of input channels. The blending controller is coupled to the blending stage for controlling operation of the blending stage. The blending stage further comprises a controllable switch for coupling an output of at least one blender of the multiple blenders to a display output of the blending stage for regular on-the-fly blending or to an offline blending memory for storing a result of an offline blending task. The blending controller comprises an input for receiving layer data describing locations and/or properties of the multiple image layers and a predictor for, based on the layer data, predicting an availability of the at least one blender. The blending controller is further operative to control the blending stage to perform the offline blending task in dependence of the predicted availability.

    摘要翻译: 一种显示控制器,包括混合台和混合控制器。 提供混合阶段用于将多个图像层混合成一个显示输出图像,并且包括用于接收多个图像层的像素数据的多个输入通道。 混合阶段还包括多个混合器,用于组合由多个输入通道中的至少两个输入通道接收的像素数据。 混合控制器耦合到混合阶段以控制混合阶段的操作。 混合阶段还包括可控开关,用于将多个搅拌器的至少一个搅拌器的输出耦合到用于常规飞行混合的混合阶段的显示输出,或者用于存储离线结果的离线混合存储器 混合任务。 混合控制器包括用于接收描述多个图像层的位置和/或属性的层数据的输入,以及用于基于层数据预测至少一个搅拌器的可用性的预测器。 混合控制器进一步操作以根据预测的可用性来控制混合阶段来执行离线混合任务。

    AUDIO UNIT AND METHOD FOR GENERATING A SAFETY CRITICAL AUDIO SIGNAL
    6.
    发明申请
    AUDIO UNIT AND METHOD FOR GENERATING A SAFETY CRITICAL AUDIO SIGNAL 有权
    用于产生安全关键音频信号的音频单元和方法

    公开(公告)号:US20150245116A1

    公开(公告)日:2015-08-27

    申请号:US14423478

    申请日:2012-08-24

    IPC分类号: H04R1/00 G08B3/00

    摘要: An audio unit, connected or connectable to a safety-critical apparatus, or integrated or integrable in the apparatus, is proposed. The audio unit may comprise a driver unit, a detection unit, and an alert unit. The driver unit may generate an analog audio signal in response to a request from the apparatus, to drive an acoustic output unit and thereby generate an acoustic signal for a user of the apparatus. The detection unit may detect the audio signal. The alert unit may generate an alert signal in response to the request if the detection unit has not detected the audio signal. It can thus be checked whether the acoustic signal is generated. A method for generating a safety critical acoustic signal is also described.

    摘要翻译: 提出了连接或可连接到安全关键设备的音频单元,或者在该装置中集成或可集成的音频单元。 音频单元可以包括驱动器单元,检测单元和警报单元。 驱动器单元可以响应于来自设备的请求而产生模拟音频信号,以驱动声输出单元,从而为该设备的用户生成声信号。 检测单元可以检测音频信号。 如果检测单元没有检测到音频信号,则警报单元可以响应于该请求而生成警报信号。 因此可以检查是否产生声信号。 还描述了一种用于产生安全关键声信号的方法。

    DISPLAY CONTROLLER WITH BLENDING STAGE
    7.
    发明申请
    DISPLAY CONTROLLER WITH BLENDING STAGE 有权
    显示控制器与混合阶段

    公开(公告)号:US20150109330A1

    公开(公告)日:2015-04-23

    申请号:US14394682

    申请日:2012-04-20

    IPC分类号: G06T11/60 G06T1/60

    摘要: A display controller comprising a blending stage and a blending controller. The blending stage is provided for blending multiple image layers into one display output image and comprises a plurality of input channels for receiving pixel data for the multiple image layers. The blending stage further comprises multiple blenders for combining the pixel data received by at least two input channels of the plurality of input channels. The blending controller is coupled to the blending stage for controlling operation of the blending stage. The blending stage further comprises a controllable switch for coupling an output of at least one blender of the multiple blenders to a display output of the blending stage for regular on-the-fly blending or to an offline blending memory for storing a result of an offline blending task. The blending controller comprises an input for receiving layer data describing locations and/or properties of the multiple image layers and a predictor for, based on the layer data, predicting an availability of the at least one blender. The blending controller is further operative to control the blending stage to perform the offline blending task in dependence of the predicted availability

    摘要翻译: 一种显示控制器,包括混合台和混合控制器。 提供混合阶段用于将多个图像层混合成一个显示输出图像,并且包括用于接收多个图像层的像素数据的多个输入通道。 混合阶段还包括多个混合器,用于组合由多个输入通道中的至少两个输入通道接收的像素数据。 混合控制器耦合到混合阶段以控制混合阶段的操作。 混合阶段还包括可控开关,用于将多个搅拌器的至少一个搅拌器的输出耦合到用于常规飞行混合的混合阶段的显示输出,或者用于存储离线结果的离线混合存储器 混合任务。 混合控制器包括用于接收描述多个图像层的位置和/或属性的层数据的输入,以及用于基于层数据预测至少一个搅拌器的可用性的预测器。 混合控制器进一步操作以根据预测的可用性来控制混合阶段来执行离线混合任务

    Data processing system and method of controlling access to a shared memory unit

    公开(公告)号:US09892088B2

    公开(公告)日:2018-02-13

    申请号:US14358049

    申请日:2011-11-24

    摘要: A data processing system comprising at least a memory unit, a first client connected to the memory unit, and a second client connected to the memory unit is proposed. The first client may comprise a first memory access unit and an information unit. The first memory access unit may read data from or write data to the memory unit at a first data rate. The information unit may update internal data correlating with a minimum required value of the first data rate. The second client may comprise a second memory access unit and a data rate limiting unit. The second memory access unit may read data from or write data to the memory unit at a second data rate. The data rate limiting unit may limit the second data rate in dependence on the internal data. The first memory access unit may, for example, read data packets sequentially from the memory unit, and the information unit may update the internal data at least per data packet. A method of controlling access to a shared memory unit is also proposed.

    MEMORY ACCESS CONTROLLER, DATA PROCESSING SYSTEM, AND METHOD FOR MANAGING DATA FLOW BETWEEN A MEMORY UNIT AND A PROCESSING UNIT
    10.
    发明申请
    MEMORY ACCESS CONTROLLER, DATA PROCESSING SYSTEM, AND METHOD FOR MANAGING DATA FLOW BETWEEN A MEMORY UNIT AND A PROCESSING UNIT 审中-公开
    存储器访问控制器,数据处理系统和用于管理存储单元和处理单元之间的数据流的方法

    公开(公告)号:US20140300615A1

    公开(公告)日:2014-10-09

    申请号:US14358051

    申请日:2011-11-24

    IPC分类号: G09G5/395 G09G5/36

    摘要: A memory access controller for managing data flow between a memory unit and a processing unit is described. The memory access controller comprises an addressing unit and an unpacking unit. The addressing unit may receive an address from said processing unit and select a data location within said memory unit in dependence on that address. The unpacking unit may read a first word from the selected data location, unpack the first word into a second word by applying a data conversion scheme which depends on the received address, and provide the second word to the processing unit. The data conversion scheme may comprise, for at least one possible address, a pixel format conversion. A data processing system and a method are also proposed.

    摘要翻译: 描述了一种用于管理存储器单元和处理单元之间的数据流的存储器存取控制器。 存储器访问控制器包括寻址单元和拆包单元。 寻址单元可以从所述处理单元接收地址,并根据该地址在所述存储器单元内选择数据位置。 解包单元可以从所选择的数据位置读取第一个字,通过应用取决于接收到的地址的数据转换方案将第一个字解码成第二个字,并将第二个字提供给处理单元。 对于至少一个可能的地址,数据转换方案可以包括像素格式转换。 还提出了一种数据处理系统和方法。