公开(公告)号：US4760432A

公开(公告)日：1988-07-26

申请号：US923867

申请日：1986-10-28

申请人： Michael Stoisiek ,  Horst Schmid ,  Helmut Strack

发明人： Michael Stoisiek ,  Horst Schmid ,  Helmut Strack

IPC分类号： H01L29/74 ,  H01L29/745 ,  H01L29/749

CPC分类号： H01L29/7408 ,  H01L29/7455

摘要： A thyristor having a pnpn semiconductor body comprising MISFET structures 9 and 12 through 16 which serve as controllable emitter base shorts formed at the edge side relative to one of the emitter layers and each of the structures is composed of a semiconductor region 9 inserted into the emitter layer which is contacted by an electrode 6 for the emitter layer 1 and also includes a subregion 12 of the adjacent base layer 2 and of an intervening channel region 13 which is formed of an edge zone of the emitter layer 1 and is also composed of a gate covering the channel region in an insulated manner. The gate also convers the subregion 12 of the base layer 2 and forms a MIS capacitor C1. A voltage generator 23 drives the gate 15 with a voltage which alternates between first and second values. At the change from the first voltage value which lies below the threshold value of the channel region 13 to the second voltage level which is close to the threshold voltage of the subregion 12 of the base layer, the thyristor ignites due to the shift in current of the MIS capacitor C1 which serves as the ignition current and, thus, when the change from the second to the first voltage occurs, the thyristor is quenched.

摘要翻译： 具有pnpn半导体本体的晶闸管包括MISFET结构9和12至16，其用作可控发射极基极短路，其形成在相对于一个发射极层的边缘侧，并且每个结构由插入发射极的半导体区域9 层，其由发射极层1的电极6接触，并且还包括相邻基极层2的子区域12和由发射极层1的边缘区域形成的中间沟道区域13，并且还由 栅极以绝缘方式覆盖沟道区域。 门也对基层2的子区域12进行通信，形成MIS电容器C1。 电压发生器23以在第一和第二值之间交替的电压驱动门15。 在从低于通道区域13的阈值的第一电压值变化到接近于基极层子区域12的阈值电压的第二电压电平的情况下，晶闸管由于电流的偏移而点燃 用作点火电流的MIS电容器C1，因此当从第二电压到第一电压的变化发生时，晶闸管被淬火。

公开(公告)号：US4942443A

公开(公告)日：1990-07-17

申请号：US370495

申请日：1982-04-21

申请人： Michael Stoisiek

发明人： Michael Stoisiek

IPC分类号： H01L29/74 ,  H01L29/749

CPC分类号： H01L29/7428 ,  H01L29/742

摘要： A power thyristor with internal current amplification has an auxilary emitter region which is contacted by an auxiliary emitter electrode. Disconnectible current paths designed as MIS structures are provided between the auxiliary emitter electrode and the base layer adjacent to the auxiliary emitter region. The current paths, which effect a stabilization in their switched-on state, are switched off for the duration of the ignition operation in order to increase the trigger sensitivity. Each MIS structure exhibits a short-circuit region inserted into the adjacent base layer spaced from the auxiliary emitter region, said short-circuit region being connected to the adjacent base layer over a conductive coating.

摘要翻译： 具有内部电流放大的功率晶闸管具有辅助发射极区域，其由辅助发射极电极接触。 在辅助发射电极和与辅助发射极区域相邻的基极层之间提供设计为MIS结构的断路电流路径。 为了提高触发灵敏度，在点火操作的持续时间内关闭影响其接通状态稳定的电流路径。 每个MIS结构具有插入到与辅助发射极区隔开的相邻基极层中的短路区域，所述短路区域在导电涂层上连接到相邻的基极层。

公开(公告)号：US06635944B2

公开(公告)日：2003-10-21

申请号：US09883477

申请日：2001-06-18

申请人： Michael Stoisiek

发明人： Michael Stoisiek

IPC分类号： H01L2900

CPC分类号： H01L29/0661 ,  H01L29/0615 ,  H01L2924/0002 ,  H01L2924/00

摘要： Component having a blocking pn junction having an edge termination structure which is formed by a further, more weakly doped region (5) and a trench (8) formed therein, said trench being filled with a dielectric. The dielectric material in the trench (8) diverts the equipotential areas from the horizontal in a very confined space in the vertical direction, with the result that the electric field can emerge from the component within a small region of the chip surface.

摘要翻译： 具有阻挡pn结的部件具有由另外更弱的掺杂区域（5）和形成在其中的沟槽（8）形成的边缘端接结构，所述沟槽填充有电介质。 沟槽（8）中的电介质材料在垂直方向的非常密闭的空间中将等电位区域从水平方向转移，结果是电场可以从芯片表面的小区域内的部件出现。

公开(公告)号：US4884114A

公开(公告)日：1989-11-28

申请号：US515175

申请日：1983-07-19

申请人： Eberhard Spenke ,  Michael Stoisiek

发明人： Eberhard Spenke ,  Michael Stoisiek

IPC分类号： H01L29/744 ,  H01L29/74 ,  H01L29/749 ,  H03K17/732

CPC分类号： H03K17/732

摘要： A thyristor has a semiconductor member with a pnpn-layer sequence, a plurality of n(p)-emitter parts, and switching transistors arranged at the edges of the n(p)-emitter parts. The switching transistors respectively include a p(n) semiconductor zone inserted in one of the n(p)-emitter parts, a partial zone of the p(n)-base, and an intermediately disposed channel zone covered by an insulated gate. Rapid and effective reduction of the electron-hole plasma flooding the p-base and n-base during quenching of the thyristor is achieved by a current source connected between electrodes for the p(n) semiconductor zones and a cathode (anode) feed line, the current source delivering an extraction current pulse.

摘要翻译： 晶闸管具有具有pnpn层序列的半导体部件，多个n（p） - 发射器部件和布置在n（p）发射器部分的边缘处的开关晶体管。 开关晶体管分别包括插入n（p） - 发射器部分之一的p（n）半导体区域，p（n） - 基极的部分区域和由绝缘栅极覆盖的中间设置的沟道区域。 通过连接在用于p（n）半导体区的电极和阴极（阳极）馈电线之间的电流源来实现在晶闸管猝灭期间快速有效地减少p基极和n-碱基的电子 - 空穴等离子体淹没， 电流源提供提取电流脉冲。

公开(公告)号：US20110102059A1

公开(公告)日：2011-05-05

申请号：US12990569

申请日：2009-05-19

申请人： Michael Stoisiek ,  Michael Gross

发明人： Michael Stoisiek ,  Michael Gross

IPC分类号： H03K3/011

CPC分类号： G05D23/19 ,  H01L21/67098 ,  H01L21/67248 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7831 ,  H03K17/145 ,  H03K2017/0806

摘要： Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network (4) of the active chip region is subdivided into several gate electrode network sectors (B1, B2, B3) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.

摘要翻译： 描述了一种用于调整由多个相同的单个单元组成的MOS功率组件的工作温度和用于执行该方法的组件的方法。 作为特征的特征在于，有源芯片区域的栅电极网络（4）被细分为几个通过隔离点彼此电隔离的栅极网络扇区（B1，B2，B3），并且每个 不同的栅极电压通过相应的触点馈送。

公开(公告)号：US20100148255A1

公开(公告)日：2010-06-17

申请号：US12593309

申请日：2008-03-26

申请人： Felix Fuernhammer ,  Christoph Ellmers ,  Thomas Uhlig ,  Michael Stoisiek

发明人： Felix Fuernhammer ,  Christoph Ellmers ,  Thomas Uhlig ,  Michael Stoisiek

IPC分类号： H01L29/78 ,  H01L29/06

CPC分类号： H01L29/0634 ,  H01L29/7816 ,  H01L29/7835

摘要： For achieving an enhanced combination of a low on-resistance at a high break-through voltage a lateral high-voltage MOS transistor comprises a plurality of doped RESURF regions of the first conductivity type within the drift region, wherein the doped RESURF regions are separated from each other by drift region sections in a first lateral direction (y), which is parallel to a substrate surface and is orthogonal to a connecting line from the source region to the drain region, and also in a depth direction, which is orthogonal to the substrate surface, such that in each of said two directions an alternating arrangement of regions of the first and second conductivity types is provided.

摘要翻译： 为了在高突变电压下实现低导通电阻的增强组合，横向高压MOS晶体管包括在漂移区内的第一导电类型的多个掺杂RESURF区域，其中掺杂的RESURF区域与 彼此相对于第一横向方向（y）的漂移区域，其平行于基板表面并且与从源极区域到漏极区域的连接线垂直，并且还与深度方向垂直，该深度方向与 使得在所述两个方向中的每一个中提供所述第一和第二导电类型的区域的交替布置。

公开(公告)号：US5473181A

公开(公告)日：1995-12-05

申请号：US314710

申请日：1994-09-29

申请人： Udo Schwalke ,  Michael Stoisiek

发明人： Udo Schwalke ,  Michael Stoisiek

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L29/78 ,  H01L27/00 ,  H01L23/544

CPC分类号： H01L27/0688 ,  H01L29/7802 ,  H01L2924/0002

摘要： In an integrated circuit arrangement having at least one power component and low-voltage components, the at least one power component is realized in a semiconductor substrate. At least one contact of the power component is arranged on a principal surface of the substrate. The contact is covered with an insulation layer at a surface of which at least one thin-film component, particularly a thin-film transistor, is provided above the contact.

摘要翻译： 在具有至少一个功率分量和低电压分量的集成电路装置中，在半导体衬底中实现该至少一个功率分量。 功率元件的至少一个触点设置在基板的主表面上。 触点被绝缘层覆盖，其表面上至少有一个薄膜部件，特别是薄膜晶体管被提供在触头上方。

公开(公告)号：US08901614B2

公开(公告)日：2014-12-02

申请号：US12990569

申请日：2009-05-19

申请人： Michael Stoisiek ,  Michael Gross

发明人： Michael Stoisiek ,  Michael Gross

IPC分类号： H01L23/52 ,  H01L29/78 ,  H01L21/67 ,  H01L29/423 ,  G05D23/19 ,  H03K17/14 ,  H03K17/08

CPC分类号： G05D23/19 ,  H01L21/67098 ,  H01L21/67248 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7831 ,  H03K17/145 ,  H03K2017/0806

摘要： Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network (4) of the active chip region is subdivided into several gate electrode network sectors (B1, B2, B3) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.

摘要翻译： 描述了一种用于调整由多个相同的单个单元组成的MOS功率组件的工作温度和用于执行该方法的组件的方法。 作为特征的特征在于，有源芯片区域的栅电极网络（4）被细分为几个通过隔离点彼此电隔离的栅极网络扇区（B1，B2，B3），并且每个 不同的栅极电压通过相应的触点馈送。

公开(公告)号：US08207031B2

公开(公告)日：2012-06-26

申请号：US12593310

申请日：2008-03-26

申请人： Christoph Ellmers ,  Thomas Uhlig ,  Felix Fuernhammer ,  Michael Stoisiek ,  Michael Gross

发明人： Christoph Ellmers ,  Thomas Uhlig ,  Felix Fuernhammer ,  Michael Stoisiek ,  Michael Gross

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L27/0922

摘要： Methods of forming, on a substrate, a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complementary to said first one are disclosed. According to one embodiment, the method includes (1) providing a substrate of a first conductivity type including a first active region for said first lateral high-voltage MOS transistor and a second active region for said second lateral high-voltage MOS transistor and (2) forming at least one first doped region of the first conductivity type in the first active region and forming in the second active region a drain extension region of the second conductivity type extending from a substrate surface to an interior of the substrate, including a concurrent implantation of dopants through openings of one and the same mask into the first and second active regions. Forming of the at least one first doped region may be a sub step of a superior step of forming a double RESURF structure in the first lateral high-voltage MOS transistor, and forming the double RESURF structure may include forming doped RESURF regions as two first doped regions, one thereof above and one thereof below the drift region of the first lateral high-voltage MOS transistor, and as two further doped regions, one thereof above and one thereof below the drain extension regions of the second lateral high-voltage MOS transistor, wherein the first doped RESURF regions have an inverse conductivity type with respect to the drift region and the further doped regions have inverse conductivity type as compared to the drain extension region.

摘要翻译： 公开了在基板上形成与所述第一横向高压MOS晶体管和第二横向高压MOS晶体管互补的方法。 根据一个实施例，该方法包括（1）提供第一导电类型的衬底，其包括用于所述第一横向高压MOS晶体管的第一有源区和用于所述第二横向高压MOS晶体管的第二有源区和（2 ）在所述第一有源区中形成所述第一导电类型的至少一个第一掺杂区域，并且在所述第二有源区域中形成从衬底表面延伸到所述衬底内部的所述第二导电类型的漏极延伸区域，所述漏极延伸区域包括同时植入 的掺杂剂通过同一掩模的开口进入第一和第二活性区域。 形成至少一个第一掺杂区域可以是在第一横向高压MOS晶体管中形成双重RESURF结构的优异步骤的子步骤，并且形成双重RESURF结构可以包括形成掺杂的RESURF区域作为两个第一掺杂 区域，其中一个位于第一横向高压MOS晶体管的漂移区以下，其中一个位于第二横向高压MOS晶体管的漏极延伸区之下，其中一个位于第二横向高压MOS晶体管的漏极延伸区之下， 其中所述第一掺杂RESURF区域相对于所述漂移区域具有反向导电类型，并且所述另外的掺杂区域与所述漏极延伸区域相比具有反向导电类型。

公开(公告)号：US20110182324A1

公开(公告)日：2011-07-28

申请号：US12993559

申请日：2009-05-19

申请人： Michael Stoisiek ,  Michael Gross

发明人： Michael Stoisiek ,  Michael Gross

IPC分类号： G01K7/26 ,  H01L23/58

CPC分类号： G01K7/16 ,  G01K2217/00 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7816 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention is intended to specify an electrical measuring method for an operating temperature and a modified component for carrying out the method which improves the monitoring of the component. Measured temperature values are intended to be delivered without any time delay and without requiring additional surfaces for temperature sensors. Location-related temperature values need to be able to be measured. The invention proposes a method for said location-related electrical measurement of the operating temperature of a likewise proposed MOS power component with a gate electrode network comprising a material whose temperature coefficient of the electrical resistance is known. The gate electrode network is divided into a plurality of measuring sections with contact point pairs which are respectively connected to contacts (71.1, 72.1; 71.2, 72.2; 71.3, 7; 72.3, 7). The contact points in each contact point pair are at a certain distance from one another, and each of the measuring sections situated between the contact point pairs is respectively electrically insulated from the other measuring sections, so that there is no electrical influencing between the measuring sections. The electrical resistances of the measuring sections are measured directly on the gate electrode network during the operation of the semiconductor power component when gate voltages are applied between the contact points of the gate electrode (4) using measuring voltages (u1, u2, u3) superimposed on the gate voltages. The electrical resistances of the measuring sections are used to determine the temperatures of the MOS semiconductor power component on the measuring sections.

摘要翻译： 本发明旨在指定用于操作温度的电测量方法和用于实施改进对部件的监视的方法的改进部件。 测量的温度值意图在没有任何时间延迟的情况下传送，而不需要额外的温度传感器表面。 需要测量位置相关的温度值。 本发明提出了一种用于所述位置相关电测量同样提出的MOS功率部件的操作温度的方法，其中栅电极网络包括其电阻温度系数已知的材料。 栅极电极网络被分成多个测量部分，其具有分别连接到触点（71.1,72.1; 71.2,72.2; 71.3,7,72.3,7）的接触点对。 每个接触点对中的接触点彼此距离一定距离，并且位于接触点对之间的每个测量部分分别与其它测量部分电绝缘，使得在测量部分 。 在使用测量电压（u1，u2，u3）叠加的栅电极（4）的接触点之间施加栅极电压时，在半导体功率分量的运行期间，在栅电极网络上直接测量测量部分的电阻 对栅极电压。 测量部分的电阻用于确定测量部分上的MOS半导体功率部件的温度。