SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING
    3.
    发明申请
    SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING 有权
    用于写入累积和分析的二次高速缓存

    公开(公告)号:US20120191904A1

    公开(公告)日:2012-07-26

    申请号:US13430613

    申请日:2012-03-26

    IPC分类号: G06F12/02 G06F12/08

    摘要: A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed herein.

    摘要翻译: 本文公开了一种高效地使用大型二级高速缓存的方法。 在某些实施例中,这种方法可以包括在二次高速缓存中累积多个数据轨道。 这些数据轨道可以包括经修改的数据和/或未修改的数据。 该方法可以确定多个数据轨道的一个子集是否构成一个完整的步幅。 在子集构成一个完整的步骤的情况下,该方法可能会从二级缓存中退出该子集。 通过降级整个步骤,该方法减少了从二级缓存中恢复数据所需的磁盘操作数。 本文还公开了相应的计算机程序产品和装置。

    SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING
    4.
    发明申请
    SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING 有权
    用于写入累积和分析的二次高速缓存

    公开(公告)号:US20110087837A1

    公开(公告)日:2011-04-14

    申请号:US12577164

    申请日:2009-10-10

    IPC分类号: G06F12/08

    摘要: A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed and claimed herein.

    摘要翻译: 本文公开了一种高效地使用大型二级高速缓存的方法。 在某些实施例中,这种方法可以包括在二次高速缓存中累积多个数据轨道。 这些数据轨道可以包括经修改的数据和/或未修改的数据。 该方法可以确定多个数据轨道的一个子集是否构成一个完整的步幅。 在子集构成一个完整的步骤的情况下,该方法可能会从二级缓存中退出该子集。 通过降级整个步骤,该方法减少了从二级缓存中恢复数据所需的磁盘操作数。 本文还公开并要求对应的计算机程序产品和装置。

    Storage application performance matching
    5.
    发明授权
    Storage application performance matching 有权
    存储应用性能匹配

    公开(公告)号:US08375180B2

    公开(公告)日:2013-02-12

    申请号:US12700964

    申请日:2010-02-05

    IPC分类号: G06F12/00

    摘要: Input/output (I/O) activity in the multiple tier storage system is monitored to collect statistical information. The statistical information is recurrently transformed into an exponential moving average (EMA) of the I/O activity having a predefined smoothing factor. Data portions in the multiple tier storage system are sorted into buckets of varying temperatures corresponding to the EMA. At least one data migration plan is recurrently generated for matching the sorted data portions to at least one of an available plurality of storage device classes. One data portion sorted into a higher temperature bucket is matched with a higher performance storage device class of the available plurality of storage device classes than another data portion sorted into a lower temperature bucket.

    摘要翻译: 监控多层存储系统中的输入/输出(I / O)活动以收集统计信息。 统计信息被循序变换成具有预定平滑因子的I / O活动的指数移动平均(EMA)。 将多层存储系统中的数据部分分类为对应于EMA的不同温度的桶。 循环地生成至少一个数据迁移计划,用于将排序的数据部分与可用的多个存储设备类中的至少一个进行匹配。 分类到较高温度桶中的一个数据部分与可分解为较低温度桶的另一数据部分的可用多个存储设备类别的更高性能的存储设备类相匹配。

    Method and system for performance enhancement via transaction verification using a counter value in a polled data storage environment
    7.
    发明授权
    Method and system for performance enhancement via transaction verification using a counter value in a polled data storage environment 失效
    通过在轮询数据存储环境中使用计数器值的事务验证来提高性能的方法和系统

    公开(公告)号:US07644201B2

    公开(公告)日:2010-01-05

    申请号:US10990882

    申请日:2004-11-17

    IPC分类号: G06F13/001

    摘要: A method of verifying the passage of a data write across a bus is provided including sending the data write from an originator across the bus to a target, counting the number of data entries received at the target with a counter, and transmitting a return echo write from the target across the bus to a return address. The method further includes attaching the counter value to other data associated with the return echo write and polling the return address. The method allows determination of the completion of a data write by comparing the number of data entries included in the data write with the counter value polled from the return address. Alternatively, in a data streaming environment the progress of a data write may be determined by comparing the number of data entries included in the data write at a select point in time with the counter value polled from the return address. Typical data entries which are counted may include, but are not limited to, bytes, words, double words, or similar data quantities.

    摘要翻译: 提供了一种验证跨总线通过数据写入的方法,包括:通过总线将数据写入发送到目标,通过计数器计数在目标处接收到的数据条目的数量,并发送返回回波写入 从目标公交车到返回地址。 该方法还包括将计数器值附加到与返回回波写入相关联的其它数据并轮询返回地址。 该方法允许通过将数据写入中包括的数据条目数与从返回地址轮询的计数值进行比较来确定数据写入的完成。 或者,在数据流环境中,可以通过将选择时间点上的数据写入中包括的数据条目的数量与从返回地址轮询的计数器值进行比较来确定数据写入的进度。 计数的典型数据条目可以包括但不限于字节,字,双字或类似的数据量。

    Coordination of multiprocessor operations with shared resources
    8.
    发明授权
    Coordination of multiprocessor operations with shared resources 失效
    多处理器操作与共享资源协调

    公开(公告)号:US07650467B2

    公开(公告)日:2010-01-19

    申请号:US12052569

    申请日:2008-03-20

    IPC分类号: G06F13/00

    CPC分类号: G06F12/0831

    摘要: In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.

    摘要翻译: 在管理多处理器操作时,第一处理器重复地读取高速缓存行,其中高速缓存行从由第一处理器和第二处理器共享的资源的共享存储器的一行缓存。 根据高速缓存一致性协议,在共享存储器线和高速缓存线之间保持一致性。 在一个方面,重复的高速缓存行读取占用第一处理器并且禁止第一处理器访问共享资源。 在另一方面,在由涉及共享资源的第二处理器完成操作之后,第二处理器将数据写入共享存储器线,以向第一处理器通知第一处理器可以访问共享资源。 作为响应,第一处理器根据高速缓存一致性协议改变高速缓存行的状态,并读取由第二处理器写入的数据。 描述和要求保护其他实施例。

    PARITY DATA MANAGEMENT SYSTEM APPARATUS AND METHOD
    9.
    发明申请
    PARITY DATA MANAGEMENT SYSTEM APPARATUS AND METHOD 有权
    道德数据管理系统的设备和方法

    公开(公告)号:US20090187786A1

    公开(公告)日:2009-07-23

    申请号:US12016037

    申请日:2008-01-17

    IPC分类号: G06F11/20

    CPC分类号: G06F11/1076 G06F2211/1035

    摘要: An apparatus for parity data management receives a write command and write data from a computing device. The apparatus also builds a parity control structure corresponding to updating a redundant disk array with the write data and stores the parity control structure in a persistent memory buffer of the computing device. The apparatus also updates the redundant disk array with the write data in accordance with a parity control map and restores the RAID controller parity map from the parity control structure as part of a data recovery operation if updating the redundant disk array with the write data is interrupted by a RAID controller failure resulting in a loss of the RAID controller parity map. In certain embodiments, the parity control structure is a RAID controller parity map.

    摘要翻译: 用于奇偶校验数据管理的装置从计算装置接收写入命令和写入数据。 该装置还构建对应于用写入数据更新冗余磁盘阵列的奇偶校验控制结构,并将奇偶校验控制结构存储在计算设备的持久存储器缓冲器中。 该设备还根据奇偶校验控制映射更新具有写数据的冗余磁盘阵列,并且作为数据恢复操作的一部分从奇偶校验控制结构恢复RAID控制器奇偶校验映射,如果用写入数据更新冗余磁盘阵列 由RAID控制器故障导致RAID控制器奇偶校验映射丢失。 在某些实施例中,奇偶校验控制结构是RAID控制器奇偶校验映射。

    Saving state data in parallel in a multi-processor system
    10.
    发明授权
    Saving state data in parallel in a multi-processor system 失效
    在多处理器系统中并行保存状态数据

    公开(公告)号:US07500141B2

    公开(公告)日:2009-03-03

    申请号:US11288714

    申请日:2005-11-29

    IPC分类号: G06F11/00

    摘要: A method, system and program product save state data in a multi-processor system. A problem in the multi-processor system is detected and a statesave thread is spawned for each processor in the system. Each statesave thread directs a processor, in parallel with the other processors to attempt to identify a component in the system having a status of “incomplete”, indicating that state data of the component remains to be offloaded. When a component having a status of “incomplete” is identified, the processor executes statesave code to offload state data from the identified component. Upon completion of the state data offload from the identified component, the processor changes the status of the component to “complete”. The foregoing processes are repeated until no components are identified in the system having a status of “incomplete”.

    摘要翻译: 方法,系统和程序产品在多处理器系统中保存状态数据。 检测到多处理器系统中的问题,并为系统中的每个处理器产生一个状态线程。 每个状态线程指示处理器与其他处理器并行,以尝试识别系统中具有“不完整”状态的组件,指示组件的状态数据仍然被卸载。 当识别出具有“不完整”状态的组件时,处理器执行状态代码以从识别的组件卸载状态数据。 在从识别的组件完成状态数据卸载后,处理器将组件的状态改变为“完成”。 重复上述处理,直到在具有“不完全”状态的系统中没有识别到​​组件。