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    Piezoelectric compositions
    1.
    发明授权
    Piezoelectric compositions 有权
    压电成分

    公开(公告)号：US08641919B2

    公开(公告)日：2014-02-04

    申请号：US12376882

    申请日：2007-08-08

    Applicant: Michael Yu ,  James E. West ,  Ilene J. Busch-Vishniac ,  Dawnielle Farrar

    Inventor： Michael Yu ,  James E. West ,  Ilene J. Busch-Vishniac ,  Dawnielle Farrar

    IPC: C08L3/00 ,  C08L79/00 ,  C08L101/00 ,  H03H9/58 ,  H01L41/22

    CPC classification number: H01L41/183 ,  H01L41/193

    Abstract: Piezoelectric compositions are provided wherein mechanical and piezoelectric properties can be separately modulated. Preferred compositions include resin blends that comprise: (a) a piezoelectrically active polymer and (b) a matrix polymer, methods of making, and use of such resin blends. Advantages of preferred resin blends of the invention can include high piezoelectricity, mechanical strength and flexibility, convenient fabrication process, and high sensitivity at high temperatures.

    Abstract translation: 提供压电组合物，其中机械和压电性能可以单独调制。 优选的组合物包括树脂共混物，其包含：（a）压电活性聚合物和（b）基质聚合物，制备和使用这种树脂共混物的方法。 本发明优选的树脂共混物的优点可包括高压电性，机械强度和柔韧性，制造工艺方便，高温下的高灵敏度。

    Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach
    3.
    发明申请
    Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach 有权
    用双井剂量法在CMOS工艺流程中形成高漏电电压公差MOSFET晶体管的方法

    公开(公告)号：US20080248623A1

    公开(公告)日：2008-10-09

    申请号：US11784721

    申请日：2007-04-09

    Applicant: Yung Chih Tsai ,  Michael Yu ,  Chih-Ping Chao ,  Chih-Sheng Chang

    Inventor： Yung Chih Tsai ,  Michael Yu ,  Chih-Ping Chao ,  Chih-Sheng Chang

    IPC: H01L21/8234

    CPC classification number: H01L21/823892 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823807 ,  Y10S438/919

    Abstract: A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of a second conductivity type opposite the first conductivity type. The step of forming the embedded well region includes simultaneously doping the embedded well region and a well region of a core regular MOS device, and simultaneously doping the embedded well region and a well region of an I/O regular MOS device, wherein the core and I/O regular MOS devices are of the first conductivity type. The method further includes forming a gate stack extending from over the embedded well region to over the well region.

    Abstract translation: 一种用于形成高电压漏极金属氧化物半导体（HVD-MOS）器件的方法包括：提供半导体衬底; 形成第一导电类型的阱区; 以及在所述半导体衬底中并且仅在所述HVD-MOS器件的漏极侧上形成嵌入阱区域，其中所述嵌入区域是与所述第一导电类型相反的第二导电类型。 形成嵌入阱区的步骤包括同时掺杂嵌入阱区和芯规则MOS器件的阱区，并同时掺杂I / O规则MOS器件的嵌入阱区和阱区，其中核和 I / O常规MOS器件是第一导电类型。 所述方法还包括形成从所述嵌入阱区域上方延伸到所述阱区域的栅极堆叠。

    Piezoelectric polymer fibers
    5.
    发明授权
    Piezoelectric polymer fibers 有权
    压电聚合物纤维

    公开(公告)号：US08946974B2

    公开(公告)日：2015-02-03

    申请号：US13057652

    申请日：2009-08-19

    Applicant: Michael Yu ,  Dawnielle Farrar ,  Wonkyu Moon ,  James West ,  Sangkyu Lee

    Inventor： Michael Yu ,  Dawnielle Farrar ,  Wonkyu Moon ,  James West ,  Sangkyu Lee

    IPC: H01L41/083 ,  D01F6/68 ,  D01D5/00 ,  G01N29/24 ,  H01L41/193 ,  H01L41/08

    CPC classification number: D01F6/68 ,  D01D5/0038 ,  G01N29/2437 ,  H01L41/082 ,  H01L41/193 ,  Y10T428/298

    Abstract: Piezoelectric fibers include a polypeptide wherein molecules of the polypeptide have electric dipole moments that are aligned such that the piezoelectric fiber provides a piezoelectric effect at an operating temperature. A piezoelectric component provides a plurality of piezoelectric fibers, each comprising an organic polymer. A method of producing piezoelectric fibers includes electrospinning a polymer solution to form a fiber and winding the fiber onto a rotating target in which the rotating target is electrically grounded. An acoustic sensor includes a plurality acoustic transducers, wherein the plurality of acoustic transducers are structured and arranged to detect a corresponding plurality of vector components of an acoustic signal, and at least one of the plurality of acoustic transducers comprises a piezoelectric fiber.

    Abstract translation: 压电纤维包括多肽，其中多肽的分子具有对准的电偶极矩，使得压电纤维在操作温度下提供压电效应。 压电元件提供多个压电纤维，每个压电纤维包含有机聚合物。 制造压电纤维的方法包括静电纺丝聚合物溶液以形成纤维，并将纤维缠绕到转动靶上，旋转靶被电接地。 声学传感器包括多个声换能器，其中多个声换能器被构造和布置成检测声信号的对应的多个矢量分量，并且多个声换能器中的至少一个包括压电光纤。

    CONTINUOUS PIEZOELECTRIC FILM INCLUDING POLAR POLYMER FIBERS
    7.
    发明申请
    CONTINUOUS PIEZOELECTRIC FILM INCLUDING POLAR POLYMER FIBERS 有权
    连续压电薄膜，包括极性聚合物纤维

    公开(公告)号：US20130229091A1

    公开(公告)日：2013-09-05

    申请号：US13785767

    申请日：2013-03-05

    Applicant: Michael Yu ,  Kailiang Ren ,  James E. West

    Inventor： Michael Yu ,  Kailiang Ren ,  James E. West

    IPC: H01L41/193 ,  H01L41/333

    CPC classification number: H01L41/193 ,  H01L41/1132 ,  H01L41/333

    Abstract: A continuous piezoelectric film can include a plurality of fibers, each fiber including a polypeptide, wherein molecules of the polypeptide have electric dipole moments that are aligned such that the piezoelectric fiber provides a piezoelectric effect. The continuous piezoelectric film has at least one piezoelectric constant d31 or d33 that is at least 1 pC/N. The continuous piezoelectric film can be prepared hot pressing a mat of aligned piezoelectric fibers.

    Abstract translation: 连续的压电膜可以包括多个纤维，每个纤维包括多肽，其中多肽的分子具有电偶极矩，使得压电纤维提供压电效应。 连续压电膜具有至少一个至少1pC / N的压电常数d31或d33。 可以制备连续压电膜热压成对压电纤维的垫。

    DISCONTINUOUS DOWNLOAD OF MEDIA FILES
    8.
    发明申请
    DISCONTINUOUS DOWNLOAD OF MEDIA FILES 有权
    不连续下载媒体文件

    公开(公告)号：US20110238747A1

    公开(公告)日：2011-09-29

    申请号：US13154233

    申请日：2011-06-06

    Applicant: Michael Yu ,  Ryan Edward Cukierman ,  Stephen Michael Lacy

    Inventor： Michael Yu ,  Ryan Edward Cukierman ,  Stephen Michael Lacy

    IPC: G06F15/16

    CPC classification number: H04N21/44012 ,  G06Q30/0242 ,  H04N21/23412 ,  H04N21/2343 ,  H04N21/4325 ,  H04N21/6581

    Abstract: Systems and methods provide for discontinuous download of media files. The system and method work within the bounds of simple, existing, open protocols and the media files served are playable by standard media playback clients. The method is driven by a request to play a media file from any location within the media file, including sections of the media file that the initial download has not yet reached. The method comprises downloading the media file in segments corresponding to the location in the media file that the user desires to view and merging the segments. The method allows for tracking of which segments have been downloaded and which have not.

    Abstract translation: 系统和方法提供媒体文件的不连续下载。 系统和方法在简单，现有，开放协议的范围内工作，并且提供的媒体文件可以由标准媒体播放客户端播放。 该方法由媒体文件中的任何位置播放媒体文件的请求驱动，包括媒体文件中尚未到达初始下载的部分。 该方法包括以与用户期望查看和合并片段的媒体文件中的位置相对应的片段下载媒体文件。 该方法允许跟踪哪些段已被下载，哪些段没有。

    Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach
    9.
    发明授权
    Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach 有权
    用双阱剂量法在CMOS工艺流程中形成高漏电电压公差MOSFET晶体管的方法

    公开(公告)号：US07718494B2

    公开(公告)日：2010-05-18

    申请号：US11784721

    申请日：2007-04-09

    Applicant: Yung Chih Tsai ,  Michael Yu ,  Chih-Ping Chao ,  Chih-Sheng Chang

    Inventor： Yung Chih Tsai ,  Michael Yu ,  Chih-Ping Chao ,  Chih-Sheng Chang

    IPC: H01L21/8234

    CPC classification number: H01L21/823892 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823807 ,  Y10S438/919

    Abstract: A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of a second conductivity type opposite the first conductivity type. The step of forming the embedded well region includes simultaneously doping the embedded well region and a well region of a core regular MOS device, and simultaneously doping the embedded well region and a well region of an I/O regular MOS device, wherein the core and I/O regular MOS devices are of the first conductivity type. The method further includes forming a gate stack extending from over the embedded well region to over the well region.

    Abstract translation: 一种用于形成高电压漏极金属氧化物半导体（HVD-MOS）器件的方法包括：提供半导体衬底; 形成第一导电类型的阱区; 以及在所述半导体衬底中并且仅在所述HVD-MOS器件的漏极侧上形成嵌入阱区域，其中所述嵌入区域是与所述第一导电类型相反的第二导电类型。 形成嵌入阱区的步骤包括同时掺杂嵌入阱区和芯规则MOS器件的阱区，并同时掺杂I / O规则MOS器件的嵌入阱区和阱区，其中核和 I / O常规MOS器件是第一导电类型。 所述方法还包括形成从所述嵌入阱区域上方延伸到所述阱区域的栅极堆叠。

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