公开(公告)号：US06922803B2

公开(公告)日：2005-07-26

申请号：US09811435

申请日：2001-03-20

申请人： Michinobu Nakao ,  Kazumi Hatayama ,  Koichiro Natsume ,  Yoshikazu Kiyoshige ,  Masaki Kouno ,  Masato Hamamoto ,  Hidefumi Yoshida ,  Tomoji Nakamura

发明人： Michinobu Nakao ,  Kazumi Hatayama ,  Koichiro Natsume ,  Yoshikazu Kiyoshige ,  Masaki Kouno ,  Masato Hamamoto ,  Hidefumi Yoshida ,  Tomoji Nakamura

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G06F11/22 ,  G11C29/10 ,  G06F11/00

CPC分类号： G01R31/3183 ,  G11C29/10

摘要： A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising means 110 to generate identical pattern sequences repeatedly and means 120 to control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test 130. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns. Because a test pattern generator is provided independently of the circuit to be tested, the problem of a prolonged design period can be eliminated, a loss in the operating speed of the circuit under test is minimized and a high fault coverage can be achieved with less hardware overhead and a smaller volume of test data.

摘要翻译： 一种半导体集成电路测试方法，其减少测试所需的数据量并有效地检测要测试的电路中的故障，该方法包括重复生成相同模式序列的装置110，以及以模式序列控制翻转位的装置120，以便 生成邻域模式序列并使用邻域模式来测试被测电路130。 相邻图案全部或部分地包括没有翻转位的图案序列，一个具有一个图案中的全部或一些翻转位的图案序列，以及以规则间隔连续的图案或图案中的全部或一些翻转的位， 相当于给定数量的图案。 由于测试模式发生器独立于要测试的电路提供，可以消除延长设计周期的问题，使被测电路的工作速度损失最小化，并且可以通过较少的硬件实现高故障覆盖 开销和较小量的测试数据。

公开(公告)号：US06484294B1

公开(公告)日：2002-11-19

申请号：US09462913

申请日：2000-01-18

申请人： Yoshikazu Kiyoshige ,  Michinobu Nakao ,  Kazumi Hatayama ,  Takashi Hotta

发明人： Yoshikazu Kiyoshige ,  Michinobu Nakao ,  Kazumi Hatayama ,  Takashi Hotta

IPC分类号： G06F1750

CPC分类号： G01R31/318583 ,  G01R31/3016

摘要： A method for designing a semiconductor integrated circuit while minimizing any increase in the area of its logic circuit under test. Circuit data about the semiconductor integrated circuit are received, and transition signal occurrence probabilities of all scanning function-equipped storage elements involved are computed by use of the circuit data. In keeping with the transition signal occurrence probabilities thus computed and based on predetermined parameters, the method permits selection of scanning function-equipped storage elements that may be replaced by delay test-ready scanning function-equipped storage elements.

摘要翻译： 一种用于设计半导体集成电路同时最小化其被测逻辑电路的面积的任何增加的方法。 接收关于半导体集成电路的电路数据，并且通过使用电路数据来计算所涉及的所有配备有扫描功能的存储元件的转换信号发生概率。 为了与由此计算出的过渡信号发生概率和基于预定参数保持一致，该方法允许选择可由具有延迟测试就绪扫描功能的存储元件代替的具有扫描功能的存储元件。

公开(公告)号：US5684729A

公开(公告)日：1997-11-04

申请号：US530471

申请日：1995-09-19

申请人： Hiromichi Yamada ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Takashi Hotta ,  Hideo Sawamoto ,  Takahiro Nishiyama ,  Yoshikazu Kiyoshige ,  Noriyasu Ido

发明人： Hiromichi Yamada ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Takashi Hotta ,  Hideo Sawamoto ,  Takahiro Nishiyama ,  Yoshikazu Kiyoshige ,  Noriyasu Ido

IPC分类号： G06F7/50 ,  G06F7/74

CPC分类号： G06F7/74 ,  G06F7/485 ,  G06F7/49947 ,  G06F7/49994

摘要： To offer a floating-point addition/subtraction processing apparatus and a method thereof, capable of shortening the computation time, the floating-point calculation processing apparatus includes an approximate shift mount predicting unit for predicting a shift amount for normalization by using the input floating-point data to be addition/subtraction processed within an error of 1 bit, a shift error detecting unit for detecting a difference between the predicted shift amount and a correct shift amount, and an bit shifter for correcting a result, obtained by normalization using the predicted shift amount, by the detected difference of the two shift amounts, wherein a round-off determination and a shift amount calculation are processed in parallel before a normalization shift processing is executed.

摘要翻译： 为了提供能够缩短计算时间的浮点加法/减法处理装置及其方法，浮点计算处理装置包括：近似移位预测单元，用于通过使用输入浮点运算处理装置预测用于归一化的移位量， 点数据在1比特的误差内进行加法/减法处理;移位误差检测单元，用于检测预测偏移量和正确移位量之间的差;以及位移移位器，用于校正结果， 移位量乘以检测到的两个移动量的差异，其中在执行归一化移位处理之前并行处理舍入确定和移位量计算。

公开(公告)号：US5410696A

公开(公告)日：1995-04-25

申请号：US32066

申请日：1993-03-16

申请人： Mitsuho Seki ,  Mitsuji Ikeda ,  Yoshikazu Kiyoshige

发明人： Mitsuho Seki ,  Mitsuji Ikeda ,  Yoshikazu Kiyoshige

IPC分类号： G06F15/16 ,  G06F9/44 ,  G06F9/50 ,  G06F15/177 ,  G06F9/38

CPC分类号： G06F8/45

摘要： In order to process a program by parallel processing using a plurality of processors, the program is divided into a plurality of partial programs. Then one or more expressions are derived, the or each expression expressing a relationship between the partial programs, such as which can be executed independently and which require the execution of another partial program. The expression or expressions can then be investigated to determine which has a desired characteristic, such as a characteristic corresponding to uniform loading of the processors. The expression can also be varied, to give more options for the selection of the expression with the desired characteristic. Then the partial programs can be distributed to the processors on the basis of the relationship corresponding to the expression which has the desired characteristic. Furthermore, when the partial programs are being executed by the processors, any processor which has completed its processing broadcasts a signal to the other processors, which may then re-assign one or more of their partial programs. In this way, parallel processing can be carried out quickly, with substantially uniform loading of the processors.

摘要翻译： 为了通过使用多个处理器的并行处理来处理程序，程序被分成多个部分程序。 然后导出一个或多个表达式，该表达式或每个表达式表示部分程序之间的关系，例如哪些可以独立执行，哪些需要执行另一个部分程序。 然后可以调查表达式或表达式以确定哪个具有期望的特性，例如对应于处理器的均匀加载的特性。 该表达式也可以变化，以给出具有所需特征的表达选择的更多选择。 然后，可以基于与具有期望特性的表达式对应的关系将部分程序分配给处理器。 此外，当处理器执行部分程序时，已经完成其处理的任何处理器向其他处理器广播信号，然后可以重新分配其部分程序中的一个或多个。 以这种方式，可以快速地执行并行处理，同时处理器的加载基本均匀。

公开(公告)号：US08433955B2

公开(公告)日：2013-04-30

申请号：US12610422

申请日：2009-11-02

申请人： Hiromichi Yamada ,  Kotaro Shimamura ,  Kesami Hagiwara ,  Yoshikazu Kiyoshige ,  Yuichi Ishiguro

发明人： Hiromichi Yamada ,  Kotaro Shimamura ,  Kesami Hagiwara ,  Yoshikazu Kiyoshige ,  Yuichi Ishiguro

IPC分类号： G06F11/00

CPC分类号： G06F11/1608 ,  G06F11/004 ,  G06F11/1641 ,  G06F11/1687 ,  G06F2201/83 ,  G06F2201/845

摘要： A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.

摘要翻译： 一种微控制器，其能够通过由多个CPU执行不同的程序来提高处理性能，并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。 提供了包括CPU和存储器在内的多个处理系统，每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。 压缩存储数据由比较器相互比较，当比较结果表示不匹配时，可以检测出异常处理。 即使当多个CPU异步执行相同的处理时，获得相同处理结果的定时也是不同的，因此压缩机进行压缩，因此可以容易地将它们的处理结果进行比较。 此外，由于在从所有CPU给出比较使能时能够进行比较器的比较，所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。

公开(公告)号：US20080022030A1

公开(公告)日：2008-01-24

申请号：US11779189

申请日：2007-07-17

申请人： Kesami Hagiwara ,  Takeshi Kataoka ,  Hisakazu Sato ,  Shunichi Iwata ,  Yoshikazu Kiyoshige ,  Akihiko Tomita

发明人： Kesami Hagiwara ,  Takeshi Kataoka ,  Hisakazu Sato ,  Shunichi Iwata ,  Yoshikazu Kiyoshige ,  Akihiko Tomita

IPC分类号： G06F13/36

CPC分类号： G06F13/364

摘要： In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit. A high-speed access is made from the second processor to the second local memory via the second local bus. The second local memory is also accessed from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit and from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit.

摘要翻译： 在多处理器中，两个本地存储器之一可以通过两个处理器之一高速访问，并且还可以由另一个处理器访问。 在多处理器中，第一和第二本地存储器经由第一和第二本地总线耦合到第一和第二处理器。 第一和第二总线桥耦合到系统总线和第一和第二本地总线。 第一和第二总线接口单元耦合到系统总线和第一和第二本地存储器。 通过第一本地总线从第一处理器到第一本地存储器进行高速访问。 第一本地存储器还通过第一局部总线，第一总线桥，系统总线以及第二总线接口单元的第一和第三端口以及经由第二本地总线从第二处理器访问第一本地存储器， 第二总线桥，系统总线，以及第一总线接口单元的第二和第三端口。 通过第二本地总线从第二处理器到第二本地存储器进行高速访问。 第二本地存储器还通过第二本地总线，第二总线桥，系统总线以及第一总线接口单元的第二和第三端口以及经由第一本地总线从第一处理器访问第二本地存储器， 第一总线桥，系统总线，以及第二总线接口单元的第一和第三端口。

公开(公告)号：US20100131741A1

公开(公告)日：2010-05-27

申请号：US12610422

申请日：2009-11-02

申请人： Hiromichi YAMADA ,  Kotaro Shimamura ,  Kesami Hagiwara ,  Yoshikazu Kiyoshige ,  Yuichi Ishiguro

发明人： Hiromichi YAMADA ,  Kotaro Shimamura ,  Kesami Hagiwara ,  Yoshikazu Kiyoshige ,  Yuichi Ishiguro

IPC分类号： G06F9/30 ,  G06F9/44 ,  G06F9/38

CPC分类号： G06F11/1608 ,  G06F11/004 ,  G06F11/1641 ,  G06F11/1687 ,  G06F2201/83 ,  G06F2201/845

摘要： A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.

摘要翻译： 一种微控制器，其能够通过由多个CPU执行不同的程序来提高处理性能，并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。 提供了包括CPU和存储器在内的多个处理系统，每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。 压缩存储数据由比较器相互比较，当比较结果表示不匹配时，可以检测出异常处理。 即使当多个CPU异步地执行相同的处理时，获得相同处理结果的定时也是不同的，因此可以容易地将它们的处理结果彼此进行比较，因为压缩是由压缩器执行的。 此外，由于在从所有CPU给出比较使能时能够进行比较器的比较，所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。

公开(公告)号：US07581054B2

公开(公告)日：2009-08-25

申请号：US11779189

申请日：2007-07-17

申请人： Kesami Hagiwara ,  Takeshi Kataoka ,  Hisakazu Sato ,  Shunichi Iwata ,  Yoshikazu Kiyoshige ,  Akihiko Tomita

发明人： Kesami Hagiwara ,  Takeshi Kataoka ,  Hisakazu Sato ,  Shunichi Iwata ,  Yoshikazu Kiyoshige ,  Akihiko Tomita

IPC分类号： G06F13/14 ,  G06F15/167

CPC分类号： G06F13/364

摘要： In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit. A high-speed access is made from the second processor to the second local memory via the second local bus. The second local memory is also accessed from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit and from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit.

摘要翻译： 在多处理器中，两个本地存储器之一可以通过两个处理器之一高速访问，并且还可以由另一个处理器访问。 在多处理器中，第一和第二本地存储器经由第一和第二本地总线耦合到第一和第二处理器。 第一和第二总线桥耦合到系统总线和第一和第二本地总线。 第一和第二总线接口单元耦合到系统总线和第一和第二本地存储器。 通过第一本地总线从第一处理器到第一本地存储器进行高速访问。 第一本地存储器还通过第一局部总线，第一总线桥，系统总线以及第二总线接口单元的第一和第三端口以及经由第二本地总线从第二处理器访问第一本地存储器， 第二总线桥，系统总线，以及第一总线接口单元的第二和第三端口。 通过第二本地总线从第二处理器到第二本地存储器进行高速访问。 第二本地存储器还通过第二本地总线，第二总线桥，系统总线以及第一总线接口单元的第二和第三端口以及经由第一本地总线从第一处理器访问第二本地存储器， 第一总线桥，系统总线，以及第二总线接口单元的第一和第三端口。

公开(公告)号：US5931895A

公开(公告)日：1999-08-03

申请号：US789430

申请日：1997-01-29

申请人： Hiromichi Yamada ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Noriyasu Ido ,  Yoshikazu Kiyoshige ,  Takahiro Nishiyama ,  Eiki Kamada

发明人： Hiromichi Yamada ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Noriyasu Ido ,  Yoshikazu Kiyoshige ,  Takahiro Nishiyama ,  Eiki Kamada

IPC分类号： G06F7/38 ,  G06F5/01 ,  G06F7/00 ,  G06F7/483 ,  G06F7/74 ,  G06F7/76 ,  G06F7/52

CPC分类号： G06F5/012 ,  G06F7/483

摘要： A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered. When no overflow takes place before the rounding process but overflow occurs after the rounding process, the result obtained by performing the normalization process and the rounding process is delivered as a final result.

摘要翻译： 一种浮点运算处理装置，具有通过从中间结果的指数的值减去归一化数的最小值的指数来生成用于归一化偏移的极限值的电路，以及生成作为归一化的归一化的电路 移位数，使中间结果的尾数所需的移位数中的较小的一个是归一化数，以及归一化移位的极限值。 浮点运算处理装置还具有电路，该电路具有用于检测在舍入处理之前的溢出条件的电路和用于在溢出的情况下产生值的电路，从而仅当预定值仅在 在舍入处理之前检测到溢出条件，但是在另一种情况下，通过执行归一化处理和舍入处理获得的结果被传送。 在四舍五入处理之前没有发生溢出，而在舍入处理后发生溢出的情况下，通过执行归一化处理和舍入处理获得的结果作为最终结果被传递。