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公开(公告)号：US07418579B2
公开(公告)日：2008-08-26
申请号：US10574315
申请日：2004-09-30
IPC分类号： G06F9/44 , H03K19/177
CPC分类号： G06F15/7867
摘要： The invention relates to a component with a large grain dynamically reconfigurable architecture for processing of data by processing units organized in rows and connected to each other through interconnections so as to enable processing in pipeline or parallel mode or in dependent rows mode. All data types may be processed and the component may process several applications at the same time. The choice of the grain, control at several levels with limited control interconnection resources and the data distribution circuit enable local or general reconfiguration of the component in one clock cycle.
摘要翻译： 本发明涉及一种具有大粒度动态可重构架构的组件，用于通过处理以行为组合并通过互连彼此连接的单元来处理数据，以便能够以流水线或并行模式或依赖行模式进行处理。 可以处理所有数据类型，并且组件可以同时处理多个应用程序。 通过有限的控制互连资源和数据分配电路可以选择多种级别的控制，从而在一个时钟周期内实现组件的局部或一般重新配置。
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公开(公告)号：US20070113054A1
公开(公告)日：2007-05-17
申请号：US10574315
申请日：2004-09-30
IPC分类号： G06F9/44
CPC分类号： G06F15/7867
摘要： The invention relates to a component with a large grain dynamically reconfigurable architecture for processing of data by processing units organized in rows and connected to each other through interconnections so as to enable processing in pipeline or parallel mode or in dependent rows mode. All data types may be processed and the component may process several applications at the same time. The choice of the grain, control at several levels with limited control interconnection resources and the data distribution circuit enable local or general reconfiguration of the component in one clock cycle.
摘要翻译： 本发明涉及一种具有大粒度动态可重构架构的组件，用于通过处理以行为组合并通过互连彼此连接的单元来处理数据，以便能够以流水线或并行模式或依赖行模式进行处理。 可以处理所有数据类型，并且组件可以同时处理多个应用程序。 通过有限的控制互连资源和数据分配电路可以选择多种级别的控制，从而在一个时钟周期内实现组件的局部或一般重新配置。
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3.发明授权公开(公告)号：US06826709B1
公开(公告)日：2004-11-30
申请号：US09763204
申请日：2001-02-20
申请人： Fabien Clermidy , Thierry Collette
发明人： Fabien Clermidy , Thierry Collette
IPC分类号： G06F1100
CPC分类号： G06F15/17343
摘要： This invention relates to a method for reconfiguring a network of parallel functional elements tolerant to the faults of these functional elements including said basic functional elements (P), spare functional elements (Sp), interconnecting elements (Cm) of these functional elements and a control unit, said method comprising: a step of positioning the functional elements of the logic network on the physical network; a routing step of programming interconnecting elements on the physical network, by choosing a maximum number of interconnecting elements which can be passed between two neighbouring processors using a shortest track search algorithm.
摘要翻译： 本发明涉及一种用于重新配置容纳这些功能元件的故障的并行功能元件的网络的方法，包括所述基本功能元件（P），备用功能元件（Sp），这些功能元件的互连元件（Cm）和控制 单元，所述方法包括：将所述逻辑网络的功能元件定位在所述物理网络上的步骤;通过选择可以在两个相邻处理器之间传递的互连元件的最大数量的最大数量的互连元件来编程所述物理网络上的互连元件的路由步骤 使用最短的跟踪搜索算法。
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4.发明授权Network of parallel processors to faults-tolerant towards said processors and reconfiguration method applicable to such a network 有权并行处理器的网络对容错所述处理器和适用于这种网络的重配置方法公开(公告)号：US06681316B1
公开(公告)日：2004-01-20
申请号：US09763164
申请日：2001-02-16
申请人： Fabien Clermidy , Thierry Collette
发明人： Fabien Clermidy , Thierry Collette
IPC分类号： G06F15173
CPC分类号： G06F11/2051 , G06F11/2025 , G06F11/2041 , G06F15/8023
摘要： This invention relates to a network of parallel elementary processors, tolerant to the faults of these processors including said elementary processors, spare elementary processors, elements interconnecting these processors and a control unit, and alternately a series of interconnecting element lines and processor lines, each processor being surrounded by four interconnecting elements, the processor lines being elementary processor lines, the last processor line being a line of spare processors, the edge elements of the network being interconnecting elements, wherein the control unit, connected to processors and interconnecting elements, sends instructions to the processors, controls the interconnecting elements, and checks the integrity of these processors.
摘要翻译： 本发明涉及一种平行的基本处理器网络，其容忍这些处理器的故障，包括所述基本处理器，备用基本处理器，互连这些处理器的元件和控制单元，以及交替地，一系列互连元件线和处理器线，每个处理器 由四个互连元件围绕，处理器线是基本处理器线，最后一个处理器线是备用处理器线，网络的边缘元件是互连元件，其中连接到处理器和互连元件的控制单元发送指令 到处理器，控制互连元件，并检查这些处理器的完整性。
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5.发明授权System on chip with interface and processing unit configurations provided by a configuration server 有权配置服务器提供接口和处理单元配置的片上系统公开(公告)号：US08189612B2
公开(公告)日：2012-05-29
申请号：US11686579
申请日：2007-03-15
IPC分类号： H04L12/00
CPC分类号： G06F15/7867
摘要： This invention relates to a system on chip for data flow type application. The system comprises a network on chip, a central controller and processing units connected to said network via associated network interfaces. A processing unit and/or its associated network interface can be configured on command from the central controller or on a command incorporated in a data packet to be processed. The network interface comprises a client module that can request a configuration server to transmit the parameters of a configuration that is unavailable in the interface. The invention also relates to a mobile terminal/ a base station comprising a base band modem implemented by such a system on chip.
摘要翻译： 本发明涉及用于数据流类型应用的片上系统。 该系统包括片上网络，中央控制器和经由相关网络接口连接到所述网络的处理单元。 处理单元和/或其相关联的网络接口可以根据来自中央控制器的命令或者包含在要处理的数据分组中的命令来配置。 网络接口包括可以请求配置服务器发送在接口中不可用的配置的参数的客户端模块。 本发明还涉及一种移动终端/基站，包括由片上系统所实现的基带调制解调器。
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公开(公告)号：US07957381B2
公开(公告)日：2011-06-07
申请号：US11372252
申请日：2006-03-08
申请人： Fabien Clermidy , Pascal Vivet , Edith Beigne
发明人： Fabien Clermidy , Pascal Vivet , Edith Beigne
IPC分类号： H04L12/28
CPC分类号： H04L12/56
摘要： This invention relates to the domain of Networks on Chips (NoC) and relates to a method of transferring data in a network on chip, particularly using an asynchronous “send/accept” type protocol.The invention also relates to a network on chip used to implement this method.
摘要翻译： 本发明涉及芯片上的网络（NoC）的领域，涉及一种在片上网络中传输数据的方法，特别是使用异步“发送/接受”类型的协议。 本发明还涉及用于实现该方法的片上网络。
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7.发明申请公开(公告)号：US20060067218A1
公开(公告)日：2006-03-30
申请号：US11234236
申请日：2005-09-26
IPC分类号： H04L12/26
摘要： The invention relates to a data processing method in a network on chip formed of a plurality of resources (310,320) capable of communicating with one another and of processing and at least one network controller (300) capable of initialising the communications in the network by initialisation of a credit system, the process comprising at least one communication step between at least one first resource (310) and at least one second resource (320), said communication step comprising: at least one emission by the first resource of a first plurality of special data or “credits” destined for the second resource, at least one receipt by the first resource of a first plurality of data to process sent by the second resource, the emission by the second data resource destined for first resource being authorised following the receipt by the second resource of credits emitted by the first resource.
摘要翻译： 本发明涉及一种由能够彼此通信的多个资源（310,320）形成的芯片上的数据处理方法以及能够通过初始化来初始化网络中的通信的至少一个网络控制器（300） 所述过程包括在至少一个第一资源（310）和至少一个第二资源（320）之间的至少一个通信步骤，所述通信步骤包括：所述第一资源的至少一个发射由第一资源 专用于第二资源的特殊数据或“信用”，第一资源的至少一个接收要由第二资源发送的第一多个数据进行处理，在接收之后被发往第一资源的第二资源的发射被授权 由第一个资源发出的第二个信用资源。
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8.发明授权公开(公告)号：US08904200B2
公开(公告)日：2014-12-02
申请号：US13263055
申请日：2009-04-06
CPC分类号： G06F9/5027 , Y02D10/22
摘要： A method for optimizing operation which is applicable to a multiprocessor integrated circuit chip. Each processor runs with a variable parameter, for example its clock frequency, and the optimization includes determination, in real time, of a characteristic data value associated with the processor (temperature, consumption, latency), transfer of the characteristic data to the other processors, calculation by each processor of various values of an optimization function depending on the characteristic data value of the block, on the characteristic data values of the other blocks, and on the variable parameter, the function being calculated for the current value of this parameter and for other possible values, selection, from among the various parameter values, of that which yields the best value for the optimization function, and application of this variable parameter to the processor for the remainder of the execution of the task.
摘要翻译： 一种适用于多处理器集成电路芯片的优化操作的方法。 每个处理器以可变参数（例如其时钟频率）运行，并且优化包括实时地确定与处理器相关联的特征数据值（温度，消耗，等待时间），将特征数据传输到其他处理器 每个处理器根据块的特征数据值，其他块的特征数据值以及可变参数对该参数的当前值计算的函数的各种优化函数的值进行计算，以及 对于其他可能的值，从各种参数值中选择产生优化函数的最佳值的参数值，以及将该可变参数应用于处理器以执行任务的剩余部分。
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9.发明授权公开(公告)号：US07733771B2
公开(公告)日：2010-06-08
申请号：US11234236
申请日：2005-09-26
摘要： A data processing method in a network on chip formed of a plurality of processors configured to communicate between one another, and at least one network controller configured to initialize communications in the network, the method including: receiving and storing in a memory by a first processor, one or more credit management configuration programs received from the network controller, and establishing a first communication between at least said first processor and at least one second processor.
摘要翻译： 一种由被配置为彼此通信的多个处理器形成的芯片上的数据处理方法，以及被配置为初始化网络中的通信的至少一个网络控制器，所述方法包括：通过第一处理器接收和存储在存储器中 ，从网络控制器接收的一个或多个信用管理配置程序，以及在至少所述第一处理器与至少一个第二处理器之间建立第一通信。
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10.发明申请公开(公告)号：US20120036375A1
公开(公告)日：2012-02-09
申请号：US13263055
申请日：2009-04-06
CPC分类号： G06F9/5027 , Y02D10/22
摘要： A method for optimizing operation which is applicable to a multiprocessor integrated circuit chip. Each processor runs with a variable parameter, for example its clock frequency, and the optimization includes determination, in real time, of a characteristic data value associated with the processor (temperature, consumption, latency), transfer of the characteristic data to the other processors, calculation by each processor of various values of an optimization function depending on the characteristic data value of the block, on the characteristic data values of the other blocks, and on the variable parameter, the function being calculated for the current value of this parameter and for other possible values, selection, from among the various parameter values, of that which yields the best value for the optimization function, and application of this variable parameter to the processor for the remainder of the execution of the task.
摘要翻译： 一种适用于多处理器集成电路芯片的优化操作的方法。 每个处理器以可变参数（例如其时钟频率）运行，并且优化包括实时地确定与处理器相关联的特征数据值（温度，消耗，等待时间），将特征数据传输到其他处理器 每个处理器根据块的特征数据值，其他块的特征数据值以及可变参数对该参数的当前值计算的函数的各种优化函数的值进行计算，以及 对于其他可能的值，从各种参数值中选择产生优化函数的最佳值的参数值，以及将该可变参数应用于处理器以执行任务的剩余部分。
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