-
公开(公告)号：US20160118293A1
公开(公告)日：2016-04-28
申请号：US14525543
申请日：2014-10-28
IPC分类号： H01L21/762 , H01L21/306 , H01L21/311 , H01L21/3105 , H01L29/06 , H01L21/02
CPC分类号： H01L21/76224 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/02274 , H01L21/02282 , H01L21/30604 , H01L21/31051 , H01L21/31053 , H01L21/31055 , H01L21/31116 , H01L21/31138 , H01L21/76202 , H01L29/0649
摘要： A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity. The higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is reached and before touching down on the silicon nitride oxidation layer. The DUO is removed and a standard chemical-mechanical polish (CMP) is performed on the silicon wafer. After the CMP step the silicon nitride is removed, exposing the silicon substrate between the field oxides.
摘要翻译： 在浅沟槽隔离（STI）被HDP氧化物填充之后，将一层部分平面化的有机硅酸盐（DUO）旋涂在硅晶片上的高密度等离子体（HDP）层上。 然后使用专门调整以特定选择性蚀刻DUO和高密度等离子体（HDP）氧化物的专门工艺来蚀刻DUO层。 晶圆形貌（有源Si区）的较高区域具有更薄的DUO，并且随着蚀刻工艺的进行，它开始蚀刻穿过这些区域（活性Si区域）中的HDP氧化物。 在达到一定深度之后并在氮化硅氧化层上触摸之前停止蚀刻工艺。 去除DUO，并在硅晶片上进行标准化学机械抛光（CMP）。 在CMP步骤之后，去除氮化硅，在场氧化物之间暴露硅衬底。
-
公开(公告)号：US09627246B2
公开(公告)日：2017-04-18
申请号：US14735359
申请日：2015-06-10
IPC分类号： H01L21/70 , H01L21/762 , H01L21/02 , H01L21/311 , H01L21/306 , H01L21/3105 , H01L29/06 , H01L21/8234
CPC分类号： H01L21/76229 , H01L21/0217 , H01L21/30604 , H01L21/31051 , H01L21/31055 , H01L21/31056 , H01L21/31111 , H01L21/76224 , H01L21/823481 , H01L21/823878 , H01L29/0649
摘要： A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.
-
公开(公告)号：US09589828B2
公开(公告)日：2017-03-07
申请号：US14525543
申请日：2014-10-28
IPC分类号： H01L21/302 , H01L21/461 , H01L21/762 , H01L29/06 , H01L21/02 , H01L21/311 , H01L21/3105 , H01L21/306
CPC分类号： H01L21/76224 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/02274 , H01L21/02282 , H01L21/30604 , H01L21/31051 , H01L21/31053 , H01L21/31055 , H01L21/31116 , H01L21/31138 , H01L21/76202 , H01L29/0649
摘要： A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity. The higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is reached and before touching down on the silicon nitride oxidation layer. The DUO is removed and a standard chemical-mechanical polish (CMP) is performed on the silicon wafer. After the CMP step the silicon nitride is removed, exposing the silicon substrate between the field oxides.
摘要翻译： 在浅沟槽隔离（STI）被HDP氧化物填充之后，将一层部分平面化的有机硅酸盐（DUO）旋涂在硅晶片上的高密度等离子体（HDP）层上。 然后使用专门调整以特定选择性蚀刻DUO和高密度等离子体（HDP）氧化物的专门工艺来蚀刻DUO层。 晶圆形貌（有源Si区）的较高区域具有更薄的DUO，并且随着蚀刻工艺的进行，它开始蚀刻穿过这些区域（活性Si区域）中的HDP氧化物。 在达到一定深度之后并在氮化硅氧化层上触摸之前停止蚀刻工艺。 去除DUO，并在硅晶片上进行标准化学机械抛光（CMP）。 在CMP步骤之后，去除氮化硅，在场氧化物之间暴露硅衬底。
-
公开(公告)号：US20170229340A1
公开(公告)日：2017-08-10
申请号：US15489379
申请日：2017-04-17
IPC分类号： H01L21/762 , H01L21/02 , H01L21/311 , H01L21/8238 , H01L29/06 , H01L21/3105
CPC分类号： H01L21/76229 , H01L21/0217 , H01L21/30604 , H01L21/31051 , H01L21/31055 , H01L21/31056 , H01L21/31111 , H01L21/76224 , H01L21/823481 , H01L21/823878 , H01L29/0649
摘要： A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.
-
公开(公告)号：US20160365272A1
公开(公告)日：2016-12-15
申请号：US14735359
申请日：2015-06-10
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/3105 , H01L29/06 , H01L21/311 , H01L21/306
CPC分类号： H01L21/76229 , H01L21/0217 , H01L21/30604 , H01L21/31051 , H01L21/31055 , H01L21/31056 , H01L21/31111 , H01L21/76224 , H01L21/823481 , H01L21/823878 , H01L29/0649
摘要： A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.
摘要翻译： 形成用于集成电路的沟槽隔离（例如，STI）的方法包括在半导体衬底上形成衬垫氧化物层，然后形成氮化物层，通过该结构进行沟槽蚀刻以形成沟槽，沉积沟槽氧化物层 在结构上形成填充沟槽，在沉积的氧化物上沉积对沟槽氧化物层具有蚀刻选择性的牺牲平坦化层，执行去除牺牲平坦化层并降低上表面中的表面变化的平坦化蚀刻工艺 对所述沟槽氧化物层进行氧化蚀刻工艺，所述氧化物蚀刻工艺对所述沟槽氧化物层有选择性以去除所述填充沟槽外部的所述沟槽氧化物层的剩余部分，以及去除所述剩余的氮化物层，使得所述剩余的氧化物填充沟槽限定沟槽 突出在半导体衬底的暴露的上表面之上的隔离结构。
-
-
-
-
搜索结果
5 条记录 (耗时 0.012 秒)
