公开(公告)号：US20170170303A1

公开(公告)日：2017-06-15

申请号：US15375094

申请日：2016-12-11

Applicant: Microchip Technology Incorporated

Inventor： Jack Wong ,  Sajid Kabeer ,  Mel Hymas ,  Santosh Murali ,  Brad Kopp

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7881

Abstract: Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.

公开(公告)号：US20190252395A1

公开(公告)日：2019-08-15

申请号：US15983461

申请日：2018-05-18

Applicant: Microchip Technology Incorporated

Inventor： James Walls ,  Mel Hymas ,  Sajid Kabeer

IPC: H01L27/11521 ,  H01L21/225 ,  H01L21/266 ,  H01L29/66 ,  H01L29/08 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/2253 ,  H01L21/266 ,  H01L27/11524 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7884

Abstract: A method is provided for forming an integrated circuit memory cell, e.g., flash memory cell. A pair of spaced-apart floating gate structures may be formed over a substrate. A non-conformal spacer layer may be formed over the structure, and may include spacer sidewall regions laterally adjacent the floating gate sidewalls. A source implant may be performed, e.g., via HVII, to define a source implant region in the substrate. The spacer sidewall region substantially prevents penetration of source implant material, such that the source implant region is self-aligned by the spacer sidewall region. The source implant material diffuses laterally to extend partially under the floating gate. Using the non-conformal spacer layer, including the spacer sidewall regions, may (a) protect the upper corner, or “tip” of the floating gate from rounding and (b) provide lateral control of the source junction edge location under each floating gate.

公开(公告)号：US10424589B2

公开(公告)日：2019-09-24

申请号：US15983461

申请日：2018-05-18

Applicant: Microchip Technology Incorporated

Inventor： James Walls ,  Mel Hymas ,  Sajid Kabeer

IPC: H01L21/225 ,  H01L21/266 ,  H01L21/28 ,  H01L27/11521 ,  H01L29/08 ,  H01L29/66 ,  H01L29/788

Abstract: A method is provided for forming an integrated circuit memory cell, e.g., flash memory cell. A pair of spaced-apart floating gate structures may be formed over a substrate. A non-conformal spacer layer may be formed over the structure, and may include spacer sidewall regions laterally adjacent the floating gate sidewalls. A source implant may be performed, e.g., via HVII, to define a source implant region in the substrate. The spacer sidewall region substantially prevents penetration of source implant material, such that the source implant region is self-aligned by the spacer sidewall region. The source implant material diffuses laterally to extend partially under the floating gate. Using the non-conformal spacer layer, including the spacer sidewall regions, may (a) protect the upper corner, or “tip” of the floating gate from rounding and (b) provide lateral control of the source junction edge location under each floating gate.

公开(公告)号：US20190207034A1

公开(公告)日：2019-07-04

申请号：US15955251

申请日：2018-04-17

Applicant: Microchip Technology Incorporated

Inventor： Sonu Daryanani ,  James Walls ,  Sajid Kabeer

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L29/167

CPC classification number: H01L29/7884 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/324 ,  H01L27/11521 ,  H01L29/167 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7885

Abstract: A method is provided for forming a split-gate memory cell having field enhancement regions in the substrate for improved cell performance. The method may include forming a pair of gate structures over a substrate, performing a source implant between the pair of gate structures to form a self-aligned source implant region in the substrate, performing a field enhancement implant process to form field enhancement implant regions, e.g., having an opposite dopant polarity as the source implant, at or adjacent lateral sides of the source implant region, and diffusing the source implant region and field enhancement implant regions to thereby define a source region with field enhanced regions at lateral edges of the source region. The field enhanced implant process may include at least one non-vertical angled implant.

公开(公告)号：US10050131B2

公开(公告)日：2018-08-14

申请号：US15375094

申请日：2016-12-11

Applicant: Microchip Technology Incorporated

Inventor： Jack Wong ,  Sajid Kabeer ,  Mel Hymas ,  Santosh Murali ,  Brad Kopp

IPC: H01L29/66 ,  H01L29/788 ,  H01L21/02 ,  H01L29/423 ,  H01L21/28

Abstract: Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.