公开(公告)号：US10861550B1

公开(公告)日：2020-12-08

申请号：US16540170

申请日：2019-08-14

Applicant: Microchip Technology Incorporated

Inventor： Sonu Daryanani ,  Bomy Chen ,  Matthew Martin

IPC: G11C11/34 ,  G11C7/00 ,  G11C16/04 ,  H01L29/423 ,  G11C16/08 ,  G11C16/34 ,  G11C16/14 ,  G11C16/10

Abstract: A memory cell having a structure of a modified flash memory cell, but configured to operate in a low voltage domain (e.g., using voltages of ≤6V amplitude for program and/or erase operations) is provided. The disclosed memory cells may be formed with dielectric layers having reduced thickness(es) as compared with conventional flash memory cells, which allows for such low voltage operation. The disclosed memory cells may be compatible with advanced, high density, low energy data computational applications. The disclosed memory cells may replace or reduce the need for RAM (e.g., SRAM or DRAM) in a conventional device, e.g., microcontroller or computer, and are thus referred to “RAM Flash” memory cells. Data retention of RAM Flash memory cells may be increased (e.g., to days, months, or years) by (a) applying a static holding voltage at selected nodes of the cell, and/or (b) periodically refreshing data stored in RAM Flash.

公开(公告)号：US20240282740A1

公开(公告)日：2024-08-22

申请号：US18215351

申请日：2023-06-28

Applicant: Microchip Technology Incorporated

Inventor： Matthew Martin ,  Bomy Chen ,  Julius Kovats

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L24/24 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/82106 ,  H01L2924/01029 ,  H01L2924/1205

Abstract: An integrated circuit (IC) package includes a bare die mounted on a substrate, and a conductive routing region formed over the bare die, the conductive routing region including a conductive routing structure and a capacitor formed in multiple conductive routing layers. The bare die includes IC circuitry, a dielectric region at least partially encapsulating the IC circuitry, and an IC contact exposed through the dielectric region. The conductive routing structure formed in the conductive routing region is conductively connected to the IC contact of the bare die. The capacitor formed in the conductive routing region includes a first capacitor electrode and a second capacitor electrode formed in one or more of the conductive routing layers, and a capacitor dielectric element formed between the first capacitor electrode and the second capacitor electrode.

公开(公告)号：US20240282723A1

公开(公告)日：2024-08-22

申请号：US18351591

申请日：2023-07-13

Applicant: Microchip Technology Incorporated

Inventor： Matthew Martin ,  Bomy Chen ,  Julius Kovats

IPC: H01L23/64 ,  H01L21/3105 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/645 ,  H01L21/3105 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/24 ,  H01L25/16 ,  H01L2224/08235 ,  H01L2224/24226 ,  H01L2924/1206

Abstract: An integrated circuit (IC) package includes a bare die mounted on a substrate, and a conductive routing region including conductive routing structure and an inductor. The conductive routing structure is conductively connected to the bare die, and includes conductive elements formed in multiple conductive routing layers in the conductive routing region. The inductive device includes a winding formed in at least one conductive routing layer of the multiple conductive routing layers.