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公开(公告)号：US20240161812A1
公开(公告)日：2024-05-16
申请号：US18415023
申请日：2024-01-17
Applicant: Micron Technology, Inc.
Inventor： Yuan He , Beau D. Barry
IPC: G11C11/4091 , G11C11/4074 , G11C11/4094 , G11C11/4097
CPC classification number: G11C11/4091 , G11C11/4074 , G11C11/4094 , G11C11/4097
Abstract: Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.
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公开(公告)号：US11824441B2
公开(公告)日：2023-11-21
申请号：US17840434
申请日：2022-06-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dong Pan , Beau D. Barry , Liang Liu
CPC classification number: H02M3/07 , G11C5/145 , G11C17/18 , H03K19/20 , G11C11/4074
Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.
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公开(公告)号：US20230005932A1
公开(公告)日：2023-01-05
申请号：US17364281
申请日：2021-06-30
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Kunal R. Parekh , Terrence B. McDaniel , Beau D. Barry
IPC: H01L27/108
Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells. Microelectronic devices, electronic systems, and additional methods are also described.
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公开(公告)号：US20210359598A1
公开(公告)日：2021-11-18
申请号：US16321769
申请日：2018-12-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dong Pan , Beau D. Barry , Liang Liu
Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.
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公开(公告)号：US20240290375A1
公开(公告)日：2024-08-29
申请号：US18409723
申请日：2024-01-10
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Beau D. Barry
IPC: G11C11/4091 , G11C5/06 , G11C11/408 , G11C11/4097
CPC classification number: G11C11/4091 , G11C5/063 , G11C11/4085 , G11C11/4097
Abstract: A microelectronic device includes a memory array structure and a control circuitry structure vertically overlying and bonded to the memory array structure. The memory array structure includes array regions respectively including memory cells, digit lines, and word lines within horizontal areas thereof. The control circuitry structure includes control circuitry regions, sense amplifier (SA) sections including SA circuitry, and sub-word line driver (SWD) sections including SWD circuitry. The control circuitry regions horizontally overlap the array regions of the memory array structure. The SA sections respectively horizontally overlap each of two of the control circuitry regions horizontally neighboring one another in a first direction. The SWD sections are respectively interposed between two other of the control circuitry regions horizontally neighboring one another in a second direction orthogonal to the first direction. Additional microelectronic devices, memory devices, and electronic systems are also described.
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Patent Agency Ranking
公开(公告)号：US20220392515A1
公开(公告)日：2022-12-08
申请号：US17887226
申请日：2022-08-12
Applicant: Micron Technology, Inc.
Inventor： Yuan He , Beau D. Barry
IPC: G11C11/4091 , G11C11/4074
Abstract: Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.
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公开(公告)号：US11443780B2
公开(公告)日：2022-09-13
申请号：US17172257
申请日：2021-02-10
Applicant: Micron Technology, Inc.
Inventor： Yuan He , Beau D. Barry , Tae H. Kim , Christopher J. Kawamura
Abstract: An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.
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公开(公告)号：US10854274B1
公开(公告)日：2020-12-01
申请号：US16584746
申请日：2019-09-26
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Adam J. Grenzebach , Timothy B. Cowles , Beau D. Barry
IPC: G11C11/4076 , G11C11/408 , G11C11/4074
Abstract: Apparatuses, systems and methods for dynamic timing of row pull-down operations are described herein. When a word line is accessed, the row decoder may drive that word line to an active voltage, and then to an intermediate voltage. The row decoder may maintain that word line at the intermediate voltage until another word line in the same group of word lines as the accessed word line receives an access command, at which point the first word line is driven to an inactive voltage. For example, if the word lines are grouped by bank, then after an access to a first word line, the first word line may be maintained at the intermediate voltage until a second wordline in the same bank as the first word line is accessed. This may help to mitigate the effect on other nearby word lines of driving a word line to the inactive voltage.
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公开(公告)号：US11935583B2
公开(公告)日：2024-03-19
申请号：US17887226
申请日：2022-08-12
Applicant: Micron Technology, Inc.
Inventor： Yuan He , Beau D. Barry
IPC: G11C7/22 , G11C11/4074 , G11C11/4091 , G11C11/4094 , G11C11/4097
CPC classification number: G11C11/4091 , G11C11/4074 , G11C11/4094 , G11C11/4097
Abstract: Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.
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公开(公告)号：US11586495B2
公开(公告)日：2023-02-21
申请号：US16929253
申请日：2020-07-15
Applicant: Micron Technology, Inc.
Inventor： Beau D. Barry
Abstract: Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.
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