公开(公告)号：US12242346B2

公开(公告)日：2025-03-04

申请号：US17937924

申请日：2022-10-04

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  Fatma Arzum Simsek-Ege

IPC: G06F11/10 ,  G11C29/00

Abstract: Global column repair with local column decoder circuitry and related apparatuses, methods, and computing systems are disclosed. An apparatus includes global column repair circuitry including column address drivers corresponding to respective ones of column planes of a memory array. The column address drivers are configured to, if enabled, drive a received column address signal to local column decoder circuitry local to respective ones of the column planes. The global column repair circuitry also includes match circuitry and data storage elements configured to store defective column addresses corresponding to defective column planes. The match circuitry is configured to compare a received column address indicated by the received column address signal to the defective column addresses and disable a column address driver corresponding to a defective column plane responsive to a determination that the received column address matches a defective column address associated with the defective column plane.

公开(公告)号：US20250044965A1

公开(公告)日：2025-02-06

申请号：US18920190

申请日：2024-10-18

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

IPC: G06F3/06 ,  G11C5/06 ,  G11C17/16

Abstract: Signaling indicative of a command to initialize a plurality of memory dies of a memory device can be received by the memory device. Initialization of a memory die of the memory device can be delayed, at the memory die and based at least in part on fuse states of an array of fuses of the memory die, by an amount of time relative to receipt of the signaling by the memory device. Delaying initialization of memory dies of the memory device in a staggered or asynchronous manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.

公开(公告)号：US20240128189A1

公开(公告)日：2024-04-18

申请号：US17968707

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer

IPC: H01L23/528 ,  H01L27/112 ,  H01L29/86

CPC classification number: H01L23/528 ,  H01L27/11206 ,  H01L29/86 ,  H01L23/53209

Abstract: An antifuse device, including a gate having a gate dielectric layer; a first doping region connected to a first end of the gate; a second doping region connected to a second end of the gate, the second end being opposite to the first end of the gate; a channel that is disposed under the gate and that connects the first doping region and the second doping region; and an interconnection jumper that electrically connects the first doping region and the second doping region.

公开(公告)号：US11869620B2

公开(公告)日：2024-01-09

申请号：US17647508

申请日：2022-01-10

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer ,  Seth A. Eichmeyer

IPC: G11C29/00 ,  G11C11/408

CPC classification number: G11C29/70 ,  G11C11/4082

Abstract: Memory devices are disclosed. A device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, microelectronic devices, semiconductor devices, and electronic systems are also disclosed.

公开(公告)号：US20230186956A1

公开(公告)日：2023-06-15

申请号：US17547574

申请日：2021-12-10

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  Eric J. Schultz

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  H01L27/088

CPC classification number: G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  H01L27/0886 ,  G06F30/392

Abstract: Sense amplifier layout designs and related apparatuses and methods. An apparatus includes a cross-coupled pair of pull-up transistors of a sense amplifier, a cross-coupled pair of pull-down transistors of the sense amplifier, and a pair of conductive lines electrically connecting the cross-coupled pair of pull-up transistors to the cross-coupled pair of pull-down transistors. The apparatus also includes a sense amplifier control transistors sharing a continuous active material with one of the cross-coupled pair of pull-up transistors or the cross-coupled pair of pull-down transistors. A method includes asserting a shared control gate terminal of sense amplifier control transistors sharing a continuous active material with the cross-coupled pair of pull-down transistors, applying a pre-charge voltage potential to the pair of conductive lines, electrically connecting memory cells to the pre-charged pair of bit lines, and amplifying electrical charges delivered to the pair of bit lines by the memory cells.

公开(公告)号：US20230176754A1

公开(公告)日：2023-06-08

申请号：US17544407

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

IPC: G06F3/06

CPC classification number: G06F3/0626 ,  G06F3/0635 ,  G06F3/0679

Abstract: A memory device includes a memory cell array and a set of fuse banks including a common fuse bank storing common bit information corresponding to a plurality of defective memory cells in the memory cell array. The memory device including a plurality of match sub-circuits corresponding to respective defective memory cells of the plurality of defective memory cells. Each match sub-circuit can be configured to provide a determination of whether a memory cell address of a memory cell of the memory cell array matches an address of the respective defective memory cell. The plurality of match sub-circuit can include a shared common bit-processing circuit that is configured to receive common bit-by-bit results of a comparison between a portion of the memory cell address and the common bit information. The common bit-processing circuit can determine whether the common bit information matches the portion of the memory cell address.

公开(公告)号：US20230074975A1

公开(公告)日：2023-03-09

申请号：US17468523

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer ,  Toshihiko Miyashita

IPC: H01L27/112 ,  G11C17/16 ,  G11C17/18

Abstract: Transistor antifuses are disclosed. An apparatus may include an antifuse that may be configurable either as a short between a first node and a second node or as an open between the first node and the second node. The antifuse may include a selection transistor and an antifuse transistor. A source or drain of the selection transistor may be electrically coupled to the first node. A gate of the selection transistor may be configured to receive a selection voltage. A gate of the antifuse transistor may be electrically coupled the other of the source or drain of the selection transistor. A source or drain of the antifuse transistor may be electrically coupled to the second node. Associated devices, systems, and methods are also disclosed.

公开(公告)号：US11114181B1

公开(公告)日：2021-09-07

申请号：US16983757

申请日：2020-08-03

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer ,  Seth A. Eichmeyer ,  Kenji Yoshida

IPC: G11C29/00 ,  G11C29/44

Abstract: Memory devices are disclosed. A memory device may include a memory array including a number of memory cells partitioned into a number of memory segments. Each of the number of memory segments may include a redundant memory-cell group configurable to be accessed instead of a defective memory-cell group of the memory segment. The memory device may also include a set of latches configurable to indicate that a redundant memory-cell group of a memory segment of the number of memory segments is to be accessed instead of a defective memory-cell group of the memory segment. The set of latches may include segment latches configurable to indicate the memory segment or a status of the set of latches. The set of latches may also include address latches configurable to indicate the defective memory-cell group within the memory segment. Related systems and methods are also disclosed.

公开(公告)号：US20210263848A1

公开(公告)日：2021-08-26

申请号：US16796860

申请日：2020-02-20

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  Alan J. Wilson

IPC: G06F12/06

Abstract: Methods, systems, and devices for modifying subsets of memory bank operating parameters are described. First global trimming information may be configured to adjust a first subset of operating parameters for a set of memory banks within a memory system. Second global trimming information may be configured to adjust a second subset of operating parameters for the set of memory banks. Local trimming information may be used to adjust one of the subsets of the operating parameters for a subset of the memory banks. To adjust one of the subsets of the operating parameters, the local trimming information may be combined with one of the first or second global trimming information to yield additional local trimming information that is used to adjust a corresponding subset of the operating parameters at the subset of the memory banks.

公开(公告)号：US11017879B1

公开(公告)日：2021-05-25

申请号：US16723532

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt ,  George Raad ,  Seth Eichmeyer ,  Dean Gans

IPC: G11C17/16 ,  G11C29/02 ,  G11C29/18 ,  G11C29/00

Abstract: Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.