公开(公告)号：US20040238889A1

公开(公告)日：2004-12-02

申请号：US10880896

申请日：2004-06-30

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  Chandra Mouli ,  Lyle Jones

IPC: H01L027/01

CPC classification number: H01L21/26506 ,  H01L21/76235 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0214 ,  H01L27/10811 ,  H01L27/10844 ,  H01L27/10873 ,  H01L27/11521 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/7846

Abstract: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

Abstract translation: 公开了一种制造绝缘体上部分硅片的工艺。 在衬底中产生深的注入区域。 在横向腔蚀刻期间，深注入区域抵抗蚀刻。 侧腔蚀刻用于部分隔离深注入区域上方的有效区域。 根据实施例，在各种处理阶段形成深注入区域。 还公开了通过该过程实现的主动装置。 还公开了一种使用有源器件的系统。

公开(公告)号：US20030203566A1

公开(公告)日：2003-10-30

申请号：US10371694

申请日：2003-02-20

Applicant: Micron Technology, Inc.

Inventor： Mark McQueen ,  Luan C. Tran ,  Chandra Mouli

IPC: H01L021/8242

CPC classification number: H01L27/10873 ,  H01L21/28123 ,  H01L27/105 ,  H01L27/10882 ,  H01L27/10894

Abstract: The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped to at least 1null1017 atoms/cm3 with n-type and p-type dopant. The invention also includes a semiconductor construction in which a doped material is over a segment of a substrate. The doped material has a first type majority dopant therein, and is electrically connected with an electrical ground. A pair of conductively-doped diffusion regions are adjacent the segment, and spaced from one another by at least a portion of the segment. The conductively-doped diffusion regions have a second type majority dopant therein. The invention also encompasses methods of forming semiconductor constructions.

Abstract translation: 本发明包括其中具有结构的DRAM阵列，其包括通过中间绝缘材料与第二材料分离的第一材料。 第一种材料与n型和p型掺杂剂掺杂至至少1×10 17个原子/ cm 3。 本发明还包括半导体结构，其中掺杂材料在衬底的一段上方。 掺杂材料在其中具有第一类型多数掺杂剂，并且与电接地电连接。 一对导电掺杂的扩散区域与该段相邻，并且通过该段的至少一部分彼此间隔开。 导电掺杂扩散区域中具有第二类型多数掺杂剂。 本发明还包括形成半导体结构的方法。

公开(公告)号：US20030190766A1

公开(公告)日：2003-10-09

申请号：US10118569

申请日：2002-04-08

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  Chandra Mouli ,  Lyle Jones

IPC: H01L021/00

CPC classification number: H01L27/10873 ,  H01L21/26506 ,  H01L21/76235 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0214 ,  H01L27/10811 ,  H01L27/10844 ,  H01L27/11521 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/7846

Abstract: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

Abstract translation: 公开了一种制造绝缘体上部分硅片的工艺。 在衬底中产生深的注入区域。 在横向腔蚀刻期间，深注入区域抵抗蚀刻。 侧腔蚀刻用于部分隔离深注入区域上方的有效区域。 根据实施例，在各种处理阶段形成深注入区域。 还公开了通过该过程实现的主动装置。 还公开了一种使用有源器件的系统。