公开(公告)号：US20030219951A1

公开(公告)日：2003-11-27

申请号：US10388721

申请日：2003-03-13

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez

IPC: H01L021/336

CPC classification number: H01L27/0222 ,  H01L21/3221

Abstract: The invention includes an array of devices and a charge pump supported by a semiconductive material substrate. A damage region is under the array, and extends less than or equal to 50% of a distance between the array and the charge pump. The invention also includes a method in which a mask is formed over a monocrystalline silicon substrate. A neutral-conductivity-type dopant is implanted through an opening in the mask and into a section of the substrate to produce a damage region. A first boundary extends around the damage region. The masking layer is removed, and epitaxial silicon is formed over the substrate. An array of devices is formed to be supported by the epitaxial silicon. The array is bounded by a second boundary. The first boundary extends less than or equal to 100 microns beyond the second boundary.

Abstract translation: 本发明包括由半导体材料基板支撑的器件阵列和电荷泵。 损伤区域在阵列之下，并且延伸小于或等于阵列和电荷泵之间距离的50％。 本发明还包括在单晶硅衬底上形成掩模的方法。 中性导电型掺杂剂通过掩模中的开口注入基底的一部分以产生损伤区域。 第一个边界围绕损伤区域延伸。 去除掩模层，并在衬底上形成外延硅。 形成阵列的器件由外延硅支撑。 阵列由第二个边界限定。 第一个边界延伸小于或等于100微米超过第二个边界。

公开(公告)号：US20030170964A1

公开(公告)日：2003-09-11

申请号：US10385132

申请日：2003-03-10

Applicant: Micron Technology, Inc.

Inventor： David Y. Kao ,  Fernando Gonzalez

IPC: H01L021/76

CPC classification number: H01L21/76235 ,  H01L21/76202 ,  H01L21/76237

Abstract: An improved LOCOS method for forming a patterned silicon dioxide field region on a substrate assembly by implanting silicon ions into a silicon substrate. The implanted silicon ions partially randomize the lattice structure of the monocrystalline silicon in the silicon substrate and increase the availability of silicon to ambient oxygen, thus increasing the rate of oxidation of the silicon substrate. The implantation of the silicon substrate with silicon ions makes oxidation faster and reduces the formation of bird's beak structures, as compared to an unimplanted silicon substrate. The method may also incorporate a nitride spacer formed at a periphery of an opening in the silicon nitride hard mask. The nitride spacer decreases straggle and the dimension of the resultant silicon dioxide field region, such that the dimensions thereof are below photolithography resolution limits. An improved shallow trench isolation region is also taught and reduces cross-talk and allows active regions to be formed closer together. The improved shallow trench isolation region is formed with a method that includes implanting silicon ions into an isolation trench followed by formation of a thermal oxide in the isolation trench that has greater lateral dimensions at the bottom of the isolation trench than at the top. A layer of silicon nitride is deposited to fill the remainder of the isolation trench and form the shallow trench isolation region.

Abstract translation: 一种用于通过将硅离子注入到硅衬底中在衬底组件上形成图案化二氧化硅场区的改进的LOCOS方法。 注入的硅离子部分地使硅衬底中的单晶硅的晶格结构随机化，并增加了硅对环境氧的可用性，从而提高了硅衬底的氧化速率。 与未植入的硅衬底相比，用硅离子注入硅衬底使氧化更快并且减少了鸟的喙结构的形成。 该方法还可以包括形成在氮化硅硬掩模中的开口的周边处的氮化物间隔物。 氮化物间隔物减小了所得二氧化硅场区的分布和尺寸，使得其尺寸低于光刻分辨率极限。 还教导了改进的浅沟槽隔离区域并减少了串扰，并且允许有源区域更靠近地形成。 改进的浅沟槽隔离区域由一种方法形成，该方法包括将硅离子注入到隔离沟槽中，随后在隔离沟槽中形成热氧化物，该隔离沟槽在隔离沟槽的底部具有比顶部更大的横向尺寸。 沉积氮化硅层以填充隔离沟槽的其余部分并形成浅沟槽隔离区域。

公开(公告)号：US20030151081A1

公开(公告)日：2003-08-14

申请号：US10372051

申请日：2003-02-21

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez

IPC: H01L027/108

CPC classification number: H01L27/10858 ,  H01L21/76838 ,  H01L27/0207 ,  H01L27/1082 ,  H01L27/10855

Abstract: Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.

公开(公告)号：US20030042512A1

公开(公告)日：2003-03-06

申请号：US09945495

申请日：2001-08-30

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez

IPC: H01L029/80

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/28273 ,  H01L21/76232 ,  H01L21/823487 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66621 ,  H01L29/7834

Abstract: The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate receptacle that may facilitate a more uniform gate oxide layer. One embodiment relates to a storage cell that is disposed in the recess along with an electrode. Another embodiment relates to a system that includes the vertical transistor or the vertical storage cell.

Abstract translation: 本发明涉及一种实现基本曲线的凹陷底部的垂直晶体管和氧化工艺。 该凹槽用作可以促进更均匀的栅极氧化物层的栅极插座。 一个实施例涉及一种与电极一起设置在凹槽中的存储单元。 另一实施例涉及一种包括垂直晶体管或垂直存储单元的系统。

公开(公告)号：US20040238889A1

公开(公告)日：2004-12-02

申请号：US10880896

申请日：2004-06-30

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  Chandra Mouli ,  Lyle Jones

IPC: H01L027/01

CPC classification number: H01L21/26506 ,  H01L21/76235 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0214 ,  H01L27/10811 ,  H01L27/10844 ,  H01L27/10873 ,  H01L27/11521 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/7846

Abstract: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

Abstract translation: 公开了一种制造绝缘体上部分硅片的工艺。 在衬底中产生深的注入区域。 在横向腔蚀刻期间，深注入区域抵抗蚀刻。 侧腔蚀刻用于部分隔离深注入区域上方的有效区域。 根据实施例，在各种处理阶段形成深注入区域。 还公开了通过该过程实现的主动装置。 还公开了一种使用有源器件的系统。

公开(公告)号：US20040185606A1

公开(公告)日：2004-09-23

申请号：US10817704

申请日：2004-03-31

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  Er-Xuan Ping

IPC: H01L021/84 ,  H01L027/12

CPC classification number: H01L27/10894 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/1203 ,  Y10S438/933

Abstract: The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.

Abstract translation: 本发明包括形成半导体电路的方法。 提供单晶硅衬底，并且形成覆盖衬底的第一部分并且留下未覆盖的第二部分的掩模。 在未覆盖部分中形成沟槽，并且至少部分地填充有半导体材料，该半导体材料包括除硅以外的元素的至少一个原子百分比。 去除掩模，并且在衬底的第一部分上形成第一半导体电路部件。 此外，第二半导体电路部件形成在至少部分地填充沟槽的半导体材料之上。 本发明还包括半导体结构。

公开(公告)号：US20020125508A1

公开(公告)日：2002-09-12

申请号：US10138458

申请日：2002-05-03

Applicant: Micron Technology, Inc.

Inventor： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

IPC: H01L021/8234

CPC classification number: H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (nullbottom electrodesnull) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

Abstract translation: 公开了一种容器电容器结构及其构造方法。 蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。 因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。 有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

公开(公告)号：US20020117704A1

公开(公告)日：2002-08-29

申请号：US09795548

申请日：2001-02-28

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez

IPC: H01L027/108

CPC classification number: H01L27/10858 ,  H01L21/76838 ,  H01L27/0207 ,  H01L27/1082 ,  H01L27/10855

Abstract: Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.

Abstract translation: 存储单元电容器的过/欠配置的制造有助于增加给定管芯区域的电容值。 共享位线接触的一对存储单元包括在衬底表面下方的第一电容器。 该对存储单元还包括第二电容器，使得第二电容器的至少一部分位于第一电容器下方。 因此，对于给定的电容器高度，这种存储单元电容器可以相对于彼此严格横向形成的存储单元电容器具有增加的表面积。 可以使用绝缘体上硅（SOI）技术来制造存储单元电容器。 存储单元电容器可用于各种存储器阵列，存储器件和电子系统。

公开(公告)号：US20040041265A1

公开(公告)日：2004-03-04

申请号：US10230938

申请日：2002-08-29

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  John K. Zahurak

IPC: H01L023/48

CPC classification number: H01L21/84 ,  H01L27/0214 ,  H01L27/10858 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.

Abstract translation: 绝缘体上硅器件具有形成在SOI的绝缘体层中的局部偏置结构。 局部偏置结构包括图案化导体，其向SOI的硅层的不同区域提供偏置信号。 导体凹陷到绝缘体层中以提供与硅层基本平坦的界面。 导体连接到偏置电压源。 在一个实施例中，提供分别连接到多个电压源的多个导体。 因此，硅层的不同区域被不同的偏置信号偏置。

公开(公告)号：US20030077913A1

公开(公告)日：2003-04-24

申请号：US10304194

申请日：2002-11-25

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  Thomas A. Figura ,  J. Brett Rolfson

IPC: H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L28/40 ,  H01L21/324 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A method for alloying a semiconductor substrate upon which wordlines enclosed in spacers have been formed, with the substrate exposed between the wordlines. A thin sealing layer is deposited over the substrate and the wordlines, the sealing layer helping to maintain the alloy in said substrate. The alloying material employed in the substrate is hydrogen and optionally monatomic hydrogen. Alloying the substrate with monatomic hydrogen may also be done after deposition of a metal layer, or at other process steps as desired.

Abstract translation: 一种半导体衬底的合金化方法，其中已经形成了封闭在间隔物中的字线，衬底暴露在字线之间。 在衬底和字线上沉积薄的密封层，密封层有助于将合金保持在所述衬底中。 在衬底中使用的合金材料是氢和任选的单原子氢。 用单原子氢合金化基底也可以在沉积金属层之后，或者根据需要在其它工艺步骤进行。