公开(公告)号：US12079082B2

公开(公告)日：2024-09-03

申请号：US17801992

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Christophe Laurent ,  Riccardo Muzzetto

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/1076

Abstract: The present disclosure relates to a method comprising the steps of defining a minimum number of parity cells for storing parity data, the minimum number of parity cells corresponding to a minimum Error Correction Code (ECC) correction capability, defining a maximum number of parity cells for storing the parity data, the maximum number of parity cells corresponding to a maximum ECC correction capability, storing payload content in a plurality of memory cells of a memory array, and, based on a current status of the memory cells storing the payload, selecting a number of parity cells to be used for storing the parity data between the minimum number and the maximum number. The payload is stored in at least part of the parity cells which are not selected to store parity data. Related memory devices and systems are also herein disclosed.

公开(公告)号：US20240221856A1

公开(公告)日：2024-07-04

申请号：US17802009

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Christophe Laurent ,  Riccardo Muzzetto

IPC: G11C29/42 ,  G11C29/52

CPC classification number: G11C29/42 ,  G11C29/52

Abstract: The present disclosure relates to a memory device comprising an array of memory cells and an operating circuit for managing the operation of the array, the operating circuit comprising an encoding unit configured to generate a codeword, the codeword comprising payload data stored in a plurality of memory cells of the array, parity data associated with the payload data stored in parity cells of the memory array, wherein a number of parity cells to be used to store the parity data is selectable based on a status of the plurality of memory cells and is related to a selected Error Correction Code (ECC) protection level, and extra payload data stored in unused parity cells, the device further comprising a decoding unit configured to perform an ECC operation on the stored codeword based on the selected ECC protection level. The encoding unit and the decoding unit comprise respective circuit portions configured to be selectively activable based on the selected ECC protection level, and each circuit portion is configured to manage a respective predetermined payload and parity quantity of the codeword.

公开(公告)号：US20240194284A1

公开(公告)日：2024-06-13

申请号：US17801467

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Christophe Laurent ,  Riccardo Muzzetto

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/52

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C29/52

Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising the steps of storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data in parity cells of the memory array, wherein a number of used parity cells is selected based on a status of the memory cells and is related to a selected Error Correction Code (ECC) correction capability, and performing an ECC operation on the plurality of memory cells, the ECC correction capability being based on the selected number of used parity cells. Related memory devices and systems are also herein disclosed.

公开(公告)号：US12288591B2

公开(公告)日：2025-04-29

申请号：US17802009

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Christophe Laurent ,  Riccardo Muzzetto

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/26 ,  G06F11/267 ,  G06F11/27 ,  G06F11/34 ,  G11C29/42 ,  G11C29/52

Abstract: The present disclosure relates to a memory device comprising an array of memory cells and an operating circuit for managing the operation of the array, the operating circuit comprising an encoding unit configured to generate a codeword, the codeword comprising payload data stored in a plurality of memory cells of the array, parity data associated with the payload data stored in parity cells of the memory array, wherein a number of parity cells to be used to store the parity data is selectable based on a status of the plurality of memory cells and is related to a selected Error Correction Code (ECC) protection level, and extra payload data stored in unused parity cells, the device further comprising a decoding unit configured to perform an ECC operation on the stored codeword based on the selected ECC protection level. The encoding unit and the decoding unit comprise respective circuit portions configured to be selectively activable based on the selected ECC protection level, and each circuit portion is configured to manage a respective predetermined payload and parity quantity of the codeword.

公开(公告)号：US12266410B2

公开(公告)日：2025-04-01

申请号：US17801467

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Christophe Laurent ,  Riccardo Muzzetto

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/52

Abstract: The present disclosure relates to operating an array of memory cells, including storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data in parity cells of the memory array, in which a number of used parity cells is selected based on a status of the memory cells and is related to a selected Error Correction Code (ECC) correction capability, and performing an ECC operation on the plurality of memory cells, the ECC correction capability being based on the selected number of used parity cells. Related memory devices and systems are also herein disclosed.

公开(公告)号：US20250061023A1

公开(公告)日：2025-02-20

申请号：US18936548

申请日：2024-11-04

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Christophe Laurent ,  Riccardo Muzzetto

IPC: G06F11/10 ,  G06F11/07

Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction capability and/or a required ECC granularity to be applied to said memory cells, and based on the updated values of the first register, executing an ECC switch command, wherein the ECC switch command is such as to vary a previously selected ECC correction capability and/or a previously selected ECC granularity, the method further comprising: updating a second register according to the varied ECC correction capability and/or ECC granularity, said second register comprising values indicating the selected ECC correction capability and the selected ECC granularity applied to the memory cells based on the current status thereof. Related apparatuses and systems are also herein disclosed.

公开(公告)号：US20240419548A1

公开(公告)日：2024-12-19

申请号：US18821642

申请日：2024-08-30

Applicant: Micron Technology, Inc.

Inventor： Christophe Laurent ,  Riccardo Muzzetto

IPC: G06F11/10

Abstract: The present disclosure relates to defining a minimum number of parity cells for storing parity data, the minimum number of parity cells corresponding to a minimum Error Correction Code (ECC) correction capability, defining a maximum number of parity cells for storing the parity data, the maximum number of parity cells corresponding to a maximum ECC correction capability, storing payload content in a plurality of memory cells of a memory array, and, based on a current status of the memory cells storing the payload, selecting a number of parity cells to be used for storing the parity data between the minimum number and the maximum number. The payload is stored in at least part of the parity cells which are not selected to store parity data. Related memory devices and systems are also herein disclosed.

公开(公告)号：US20240412768A1

公开(公告)日：2024-12-12

申请号：US18808718

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Christophe Laurent ,  Riccardo Muzzetto

IPC: G11C11/22 ,  G11C7/10 ,  G11C16/34

Abstract: The present disclosure includes apparatuses, methods, and systems for unbalanced programmed data states in memory. An embodiment includes a memory having a group of memory cells, and circuitry configured to determine a quantity of the memory cells of the group to program to a first data state, wherein the determined quantity of memory cells is less than or greater than half of the memory cells of the group, program the determined quantity of the memory cells of the group to the first data state, and program a remaining quantity of the memory cells of the group to a second data state.

公开(公告)号：US12135610B2

公开(公告)日：2024-11-05

申请号：US17802053

申请日：2021-09-23

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Christophe Laurent ,  Riccardo Muzzetto

IPC: G06F11/10 ,  G06F11/07

Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction capability and/or a required ECC granularity to be applied to said memory cells, and based on the updated values of the first register, executing an ECC switch command, wherein the ECC switch command is such as to vary a previously selected ECC correction capability and/or a previously selected ECC granularity, the method further comprising: updating a second register according to the varied ECC correction capability and/or ECC granularity, said second register comprising values indicating the selected ECC correction capability and the selected ECC granularity applied to the memory cells based on the current status thereof. Related apparatuses and systems are also herein disclosed.

公开(公告)号：US20130283121A1

公开(公告)日：2013-10-24

申请号：US13846538

申请日：2013-03-18

Applicant: Micron Technology, Inc.

Inventor： Christophe Laurent ,  Paolo Amato ,  Marco Sforzin ,  Corrado Villa

IPC: H03M13/29

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/2909

Abstract: A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. In some embodiments, the check word may be generated by inverting one or more bits of an intermediate check word. Other embodiments may be described and claimed.

Abstract translation: 公开了一种写入单向非易失性存储单元的存储器阵列和方法，其中用户数据字被转换为内部数据字，并根据小区编码方案写入一个或多个单向数据存储单元。 可以生成对应于内部数据字的检查字。 在一些实施例中，可以通过反转中间检查字的一个或多个位来产生检验字。 可以描述和要求保护其他实施例。