公开(公告)号：US20240338149A1

公开(公告)日：2024-10-10

申请号：US18607283

申请日：2024-03-15

Applicant: Micron Technology, Inc.

Inventor： Chun-Yi Liu ,  Ameen D. Akel ,  Lance P. Johnson

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673

Abstract: Methods, systems, and devices for schedule memory are described. Specifically, techniques are described for a memory interface between a host system and memory (e.g., a tightly coupled memory). For example, a memory interface block (MIB) between the host system and the memory system may schedule access operations performed by the memory system, schedule and perform error control operations, schedule and perform media management operations, as well as schedule and perform other operations. The use of such a MIB may enable the improvement of the memory system by reducing latency and increasing efficiency of memory accesses, while reducing impacts on the architecture and design of the host system.

公开(公告)号：US20250036316A1

公开(公告)日：2025-01-30

申请号：US18771865

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Chun-Yi Liu ,  Ameen D. Akel

IPC: G06F3/06

Abstract: Methods, systems, and devices for management command techniques for stacked memory architectures are described. For example, a system may be configured to support management command signaling between a controller (e.g., of a host system) and interface circuitry (e.g., of a memory system) of a first semiconductor die that is configured for accessing one or more memory arrays (e.g., of the memory system) of one or more second semiconductor dies. The interface circuitry may be configured to schedule or otherwise determine that a management operation is to be performed, and may indicate a request to the controller to schedule aspects of the management operation. In response, the controller may indicate one or more commands to the interface circuitry to perform the management operation.

公开(公告)号：US20250045389A1

公开(公告)日：2025-02-06

申请号：US18763983

申请日：2024-07-03

Applicant: Micron Technology, Inc.

Inventor： Chun-Yi Liu ,  Lance P. Johnson ,  Nathan A. Eckel ,  James Brian Johnson

IPC: G06F21/55

Abstract: Methods, systems, and devices for row hammer mitigation reliability in stacked memory architectures are described. A spare counter may be implemented at a first interface block of a logic die to enable increased reliability and efficiency in row hammer mitigation. The first interface block may use a spare counter in case of an error associated with a counter at a memory array die. A second interface block of an array die may identify an error associated with a counter of a memory array and may transmit an indication of the error to the first interface block. The first interface block may receive the indication and may activate a spare counter to track access operations on (e.g., activations of) the row based on the indication. The first interface block may use the spare counter to evaluate whether to transmit refresh signaling to the second interface block for row hammer mitigation.

公开(公告)号：US20250045388A1

公开(公告)日：2025-02-06

申请号：US18763963

申请日：2024-07-03

Applicant: Micron Technology, Inc.

Inventor： Nathan A. Eckel ,  Chun-Yi Liu ,  Lance P. Johnson ,  James Brian Johnson ,  Yang Lu

IPC: G06F21/55

Abstract: Methods, systems, and devices for row hammer mitigation for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute operations for row hammer mitigation across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform row hammer mitigation operations. The second die may implement counters to track quantities of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.

公开(公告)号：US20240404581A1

公开(公告)日：2024-12-05

申请号：US18667791

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Brent Keeth ,  James Brian Johnson ,  Chun-Yi Liu ,  Shivasankar Gunasekaran ,  Paul A. Laberge ,  Gregory A. King ,  Sai Krishna Mylavarapu ,  Su Wei Lim ,  Nathan A. Eckel ,  Lance P. Johnson ,  Nathan D. Henningson

IPC: G11C11/4093 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: Methods, systems, and devices for interface techniques for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute memory access circuitry among multiple semiconductor dies of a stack. A first die of the system may include logic circuitry operable to configure a set of multiple first interface blocks of the first die. Each first interface block may include circuitry operable to communicate with one or more second interface blocks of one or more second dies of the system to access a respective set of one or more memory arrays of the one or more second dies. In some examples, the system may include a respective controller for each first interface block to support access operations via the first interface block. The system may also include non-volatile storage, one or more sensors, or a combination thereof to support various operations of the system.