公开(公告)号：US11741012B2

公开(公告)日：2023-08-29

申请号：US17066432

申请日：2020-10-08

Applicant: Micron Technology, Inc.

Inventor： John Leidel ,  Richard C Murphy

IPC: G06F12/0817 ,  G06F13/40 ,  G06F13/16 ,  G11C8/12 ,  G11C5/02 ,  H01L25/10

CPC classification number: G06F12/0817 ,  G06F12/0828 ,  G06F13/16 ,  G06F13/1663 ,  G06F13/40 ,  G06F13/4022 ,  G11C5/025 ,  G11C8/12 ,  H01L25/105 ,  G06F2212/622 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.

公开(公告)号：US20210125649A1

公开(公告)日：2021-04-29

申请号：US17066422

申请日：2020-10-08

Applicant: Micron Technology, Inc.

Inventor： Richard C Murphy

IPC: G11C8/12 ,  G11C5/02 ,  G06F12/02 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/1072

Abstract: A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.

公开(公告)号：US20240256473A1

公开(公告)日：2024-08-01

申请号：US18630400

申请日：2024-04-09

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Frank F Ross ,  Richard C Murphy

IPC: G06F13/16 ,  G06N3/004 ,  H01L25/065 ,  H01L25/18

CPC classification number: G06F13/1668 ,  G06N3/004 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.

公开(公告)号：US11908546B2

公开(公告)日：2024-02-20

申请号：US17066422

申请日：2020-10-08

Applicant: Micron Technology, Inc.

Inventor： Richard C Murphy

IPC: G06F12/02 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/1072 ,  G06F12/084 ,  G11C8/12 ,  G11C5/02

CPC classification number: G11C8/12 ,  G06F12/0284 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/1072 ,  G11C5/02 ,  G11C5/025 ,  G06F12/084 ,  G06F12/0824 ,  G06F2212/1032 ,  G06F2212/1048 ,  G06F2212/251 ,  G06F2212/3042

Abstract: A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.

公开(公告)号：US11989141B2

公开(公告)日：2024-05-21

申请号：US17131217

申请日：2020-12-22

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Frank F Ross ,  Richard C Murphy

IPC: G06F13/16 ,  G06N3/004 ,  H01L25/065 ,  H01L25/18

CPC classification number: G06F13/1668 ,  G06N3/004 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.

公开(公告)号：US10825496B2

公开(公告)日：2020-11-03

申请号：US14706490

申请日：2015-05-07

Applicant: Micron Technology, Inc.

Inventor： Richard C Murphy

IPC: G06F12/02 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/1072 ,  G06F12/084 ,  G11C8/12 ,  G11C5/02

Abstract: A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.