Termination for single-ended mode

    公开(公告)号:US11804261B2

    公开(公告)日:2023-10-31

    申请号:US17662325

    申请日:2022-05-06

    Abstract: This document describes apparatuses and techniques for termination for single-ended (SE) mode operation of a memory device. In various aspects, a termination circuit can terminate an unused signal line of a differential pair to a ground or power rail using a switch element when operating in the SE mode. The termination circuit may also disconnect the unused signal line from a first input of a differential amplifier and connect a reference voltage to the first input of the differential amplifier. Based on the reference voltage, the differential amplifier amplifies an SE signal received using another signal line of the differential pair at a second input of the differential amplifier to provide a clock signal for memory operations. Thus, the termination circuit may reduce an amount by which noise associated with the unused signal line affects the differential amplifier when the memory device operates in SE mode.

    Termination for Single-Ended Mode

    公开(公告)号:US20220358994A1

    公开(公告)日:2022-11-10

    申请号:US17662325

    申请日:2022-05-06

    Abstract: This document describes apparatuses and techniques for termination for single-ended (SE) mode operation of a memory device. In various aspects, a termination circuit can terminate an unused signal line of a differential pair to a ground or power rail using a switch element when operating in the SE mode. The termination circuit may also disconnect the unused signal line from a first input of a differential amplifier and connect a reference voltage to the first input of the differential amplifier. Based on the reference voltage, the differential amplifier amplifies an SE signal received using another signal line of the differential pair at a second input of the differential amplifier to provide a clock signal for memory operations. Thus, the termination circuit may reduce an amount by which noise associated with the unused signal line affects the differential amplifier when the memory device operates in SE mode.

    Apparatuses And Methods For Setting A Duty Cycle Adjuster For Improving Clock Duty Cycle

    公开(公告)号:US20200381029A1

    公开(公告)日:2020-12-03

    申请号:US16995568

    申请日:2020-08-17

    Inventor: Kang Yong Kim

    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

    METHOD, CIRCUIT AND SYSTEM FOR DETECTING A LOCKED STATE OF A CLOCK SYNCHRONIZATION CIRCUIT
    6.
    发明申请
    METHOD, CIRCUIT AND SYSTEM FOR DETECTING A LOCKED STATE OF A CLOCK SYNCHRONIZATION CIRCUIT 审中-公开
    用于检测时钟同步电路的锁定状态的方法,电路和系统

    公开(公告)号:US20150130521A1

    公开(公告)日:2015-05-14

    申请号:US14599265

    申请日:2015-01-16

    CPC classification number: H03L7/08 H03L7/0802 H03L7/0812 H03L7/095

    Abstract: Locked state detection circuits, devices, systems, and methods for detecting a locked or synchronized state of a clock synchronization circuit are described. Detection of a locked state includes a circuit including a phase detector configured to generate a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal. The circuit further includes a trend detector operably coupled to the delay adjustment signal and configured to generate a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.

    Abstract translation: 描述了用于检测时钟同步电路的锁定或同步状态的锁定状态检测电路,设备,系统和方法。 检测锁定状态包括电路,该电路包括相位检测器,该相位检测器被配置为响应于表示外部时钟信号的前向路径信号与表示输出时钟信号的反馈路径信号的比较而产生延迟调整信号。 电路还包括可操作地耦合到延迟调整信号并被配置为产生指示外部时钟信号和输出时钟信号之间的同相稳态的锁定信号的趋势检测器。

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