公开(公告)号：US08644095B2

公开(公告)日：2014-02-04

申请号：US13758610

申请日：2013-02-04

Applicant: Micron Technology, Inc.

Inventor： Kang Yong Kim ,  Chulmin Jung

IPC: G11C7/00 ,  G11C7/02

CPC classification number: G11C7/1096 ,  G11C7/00 ,  G11C7/02 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4097 ,  G11C13/004 ,  H03F3/16

Abstract: An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.

Abstract translation: 输入 - 输出线路读出放大器被配置为通过输入 - 输出信号线将输入数据信号驱动到输出驱动器电路，输入 - 输出线路读出放大器具有输出驱动级，其具有多个不同的可编程输出驱动能力，以定制 读出放大器的输出驱动。

公开(公告)号：US11804261B2

公开(公告)日：2023-10-31

申请号：US17662325

申请日：2022-05-06

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Hyunyoo Lee ,  Kang Yong Kim

IPC: G11C11/4093 ,  G06F13/40 ,  G11C11/4076 ,  H03F3/45 ,  H03K19/00

CPC classification number: G11C11/4093 ,  G06F13/4022 ,  G11C11/4076 ,  H03F3/45 ,  H03K19/0005 ,  H03F2203/45151

Abstract: This document describes apparatuses and techniques for termination for single-ended (SE) mode operation of a memory device. In various aspects, a termination circuit can terminate an unused signal line of a differential pair to a ground or power rail using a switch element when operating in the SE mode. The termination circuit may also disconnect the unused signal line from a first input of a differential amplifier and connect a reference voltage to the first input of the differential amplifier. Based on the reference voltage, the differential amplifier amplifies an SE signal received using another signal line of the differential pair at a second input of the differential amplifier to provide a clock signal for memory operations. Thus, the termination circuit may reduce an amount by which noise associated with the unused signal line affects the differential amplifier when the memory device operates in SE mode.

公开(公告)号：US20220358994A1

公开(公告)日：2022-11-10

申请号：US17662325

申请日：2022-05-06

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Hyunyoo Lee ,  Kang Yong Kim

IPC: G11C11/4093 ,  H03K19/00 ,  H03F3/45 ,  G11C11/4076 ,  G06F13/40

Abstract: This document describes apparatuses and techniques for termination for single-ended (SE) mode operation of a memory device. In various aspects, a termination circuit can terminate an unused signal line of a differential pair to a ground or power rail using a switch element when operating in the SE mode. The termination circuit may also disconnect the unused signal line from a first input of a differential amplifier and connect a reference voltage to the first input of the differential amplifier. Based on the reference voltage, the differential amplifier amplifies an SE signal received using another signal line of the differential pair at a second input of the differential amplifier to provide a clock signal for memory operations. Thus, the termination circuit may reduce an amount by which noise associated with the unused signal line affects the differential amplifier when the memory device operates in SE mode.

公开(公告)号：US20130141993A1

公开(公告)日：2013-06-06

申请号：US13758610

申请日：2013-02-04

Applicant: Micron Technology, Inc.

Inventor： Kang Yong Kim ,  Chulmin Jung

IPC: G11C7/06 ,  H03F3/16

CPC classification number: G11C7/1096 ,  G11C7/00 ,  G11C7/02 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4097 ,  G11C13/004 ,  H03F3/16

Abstract: An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.

公开(公告)号：US20200381029A1

公开(公告)日：2020-12-03

申请号：US16995568

申请日：2020-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang Yong Kim

IPC: G11C7/22 ,  G11C7/10 ,  H03K5/156 ,  G11C11/4076

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

公开(公告)号：US20150130521A1

公开(公告)日：2015-05-14

申请号：US14599265

申请日：2015-01-16

Applicant: Micron Technology, Inc.

Inventor： Tyler Gomm ,  Kang Yong Kim ,  Scott Smith ,  Jongtae Kwak

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/0802 ,  H03L7/0812 ,  H03L7/095

Abstract: Locked state detection circuits, devices, systems, and methods for detecting a locked or synchronized state of a clock synchronization circuit are described. Detection of a locked state includes a circuit including a phase detector configured to generate a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal. The circuit further includes a trend detector operably coupled to the delay adjustment signal and configured to generate a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.

Abstract translation: 描述了用于检测时钟同步电路的锁定或同步状态的锁定状态检测电路，设备，系统和方法。 检测锁定状态包括电路，该电路包括相位检测器，该相位检测器被配置为响应于表示外部时钟信号的前向路径信号与表示输出时钟信号的反馈路径信号的比较而产生延迟调整信号。 电路还包括可操作地耦合到延迟调整信号并被配置为产生指示外部时钟信号和输出时钟信号之间的同相稳态的锁定信号的趋势检测器。