公开(公告)号：US09263095B2

公开(公告)日：2016-02-16

申请号：US13953495

申请日：2013-07-29

Applicant: Micron Technology, Inc.

Inventor： Kunal Parekh ,  David Hwang ,  Wen Kuei Huang ,  Kuo Chen Wang ,  Ching Kai Lin

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/405 ,  H01L29/66 ,  H01L29/78 ,  G11C5/02 ,  H01L27/105

CPC classification number: G11C5/06 ,  G11C5/025 ,  G11C11/405 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10879 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

Abstract: A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.

公开(公告)号：US20130314967A1

公开(公告)日：2013-11-28

申请号：US13953495

申请日：2013-07-29

Applicant: Micron Technology, Inc.

Inventor： Kunal Parekh ,  David Hwang ,  Wen Kuei Huang ,  Kuo Chen Wang ,  Ching Kai Lin

IPC: G11C5/06 ,  H01L27/105 ,  G11C5/02

CPC classification number: G11C5/06 ,  G11C5/025 ,  G11C11/405 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10879 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

Abstract: A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.

Abstract translation: 具有存储单元的存储器阵列及其形成方法。 存储器阵列可以具有形成在第一水平平面体积中的掩埋数字线，形成在第一水平平面体积上方的第二水平平面体积中的字线和形成在垂直存取装置（例如finFET）的顶部上的存储装置， 在第二水平平面体积之上的第三水平平面体积。 存储器阵列可以具有4F2架构，其中每个存储器单元包括两个垂直存取设备，每个垂直存取设备耦合到单个存储设备。

公开(公告)号：US09287271B2

公开(公告)日：2016-03-15

申请号：US14699350

申请日：2015-04-29

Applicant: Micron Technology, Inc.

Inventor： Kuo Chen Wang ,  Sriraj Manavalan ,  Wei Ming Liao

IPC: H01L21/8239 ,  H01L27/108 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/10876 ,  H01L27/10808 ,  H01L27/10823 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.

公开(公告)号：US20150236023A1

公开(公告)日：2015-08-20

申请号：US14699350

申请日：2015-04-29

Applicant: Micron Technology, Inc.

Inventor： Kuo Chen Wang ,  Sriraj Manavalan ,  Wei Ming Liao

IPC: H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10808 ,  H01L27/10823 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.

Abstract translation: 垂直晶体管器件包括与绝缘隔离线相邻的有源区线。 掩埋数据/感测线相对于有源区线和介质隔离线倾斜地倾斜。 一对栅极线位于掩埋数据/感测线之外，并且相对于有源区线和介电隔离线的倾斜角度。 垂直晶体管沟道区域在该对栅极线之间的有效区域内。 外部源极/漏极区域在沟道区域上方的有源区域中，并且内部源极/漏极区域在沟道区域下方的有源区域中。 内部源极/漏极区域电耦合到掩埋的数据/感测线。 考虑形成多个垂直晶体管器件的方法也考虑了其它器件和结构。