公开(公告)号：US20200350496A1

公开(公告)日：2020-11-05

申请号：US16934844

申请日：2020-07-21

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Kunal Parekh

IPC: H01L45/00 ,  H01L27/24

Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

公开(公告)号：US20240395326A1

公开(公告)日：2024-11-28

申请号：US18652288

申请日：2024-05-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Paolo Tessariol ,  Richard J. Hill ,  Aaron S. Yip ,  Kunal Parekh

IPC: G11C16/04 ,  G11C5/06 ,  H01L29/788 ,  H01L29/792 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Memory array structures might include a data line, a common source, and a plurality of sub-blocks of memory cells selectively connected to the data line and to the common source. Sub-blocks of memory cells might include memory cells formed to be around channel material structures, and might include isolation of source-side select lines of adjacent sub-blocks of memory cells. Methods are included for forming such memory array structures.

公开(公告)号：US10971683B2

公开(公告)日：2021-04-06

申请号：US16934844

申请日：2020-07-21

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Kunal Parekh

IPC: H01L45/00 ,  H01L27/24

Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

公开(公告)号：US10756265B2

公开(公告)日：2020-08-25

申请号：US16185161

申请日：2018-11-09

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Kunal Parekh

IPC: H01L45/00 ,  H01L27/24

Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

公开(公告)号：US20190097129A1

公开(公告)日：2019-03-28

申请号：US16185161

申请日：2018-11-09

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Kunal Parekh

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L45/1691

Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

公开(公告)号：US10164178B2

公开(公告)日：2018-12-25

申请号：US15462618

申请日：2017-03-17

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Kunal Parekh

IPC: H01L27/24 ,  H01L45/00

Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

公开(公告)号：US20140231894A1

公开(公告)日：2014-08-21

申请号：US14265928

申请日：2014-04-30

Applicant: Micron Technology, Inc.

Inventor： Kunal Parekh ,  Ceredig Roberts ,  Thy Tran ,  Jim Jozwiak ,  David Hwang

IPC: H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10885

Abstract: A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.

Abstract translation: 公开了一种用于形成具有埋设的访问线（例如字线）和布置在垂直单元触点下方的掩埋数据/感测线（例如，数字线）的存储器件的方法。 掩埋字线可以在沿第一方向延伸的衬底中形成沟槽，并且掩埋的数字线可以由垂直于第一方向的第二方向延伸的衬底中的沟槽形成。 埋置的数字线可以通过设置在数字线和硅衬底之间的数字线接触件耦合到硅侧壁。

公开(公告)号：US20140138604A1

公开(公告)日：2014-05-22

申请号：US13683418

申请日：2012-11-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu ,  Kunal Parekh

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L45/1691

Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

Abstract translation: 在一些实施例中，集成电路包括填充集成电路中形成的开口的窄的垂直延伸柱。 在一些实施例中，开口可以包含相变材料以形成相变存储器单元。 支柱所占据的开口可以使用在不同垂直水平上形成的牺牲材料（例如间隔物）的交叉线来限定。 材料线可以通过允许形成非常细线的沉积工艺形成。 选择性地去除在线交叉点处的暴露材料以形成具有由线的宽度确定的尺寸的开口。 开口可以例如用相变材料填充。

公开(公告)号：US20170256710A1

公开(公告)日：2017-09-07

申请号：US15462618

申请日：2017-03-17

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Kunal Parekh

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L45/1691

Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

公开(公告)号：US20130314967A1

公开(公告)日：2013-11-28

申请号：US13953495

申请日：2013-07-29

Applicant: Micron Technology, Inc.

Inventor： Kunal Parekh ,  David Hwang ,  Wen Kuei Huang ,  Kuo Chen Wang ,  Ching Kai Lin

IPC: G11C5/06 ,  H01L27/105 ,  G11C5/02

CPC classification number: G11C5/06 ,  G11C5/025 ,  G11C11/405 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10879 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

Abstract: A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.

Abstract translation: 具有存储单元的存储器阵列及其形成方法。 存储器阵列可以具有形成在第一水平平面体积中的掩埋数字线，形成在第一水平平面体积上方的第二水平平面体积中的字线和形成在垂直存取装置（例如finFET）的顶部上的存储装置， 在第二水平平面体积之上的第三水平平面体积。 存储器阵列可以具有4F2架构，其中每个存储器单元包括两个垂直存取设备，每个垂直存取设备耦合到单个存储设备。