公开(公告)号：US12032834B2

公开(公告)日：2024-07-09

申请号：US17959131

申请日：2022-10-03

Applicant: Micron Technology, Inc.

Inventor： Joshua E. Alzheimer ,  Mow Yiak Goh ,  Loren J. Wooley

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0673 ,  G06F11/1044

Abstract: Memory with address-selectable data poisoning circuitry is disclosed herein. In one embodiment, a memory device comprises circuitry operably connected to a memory array. The circuitry can include memory row address registers and/or memory column address registers. Standard access commands or mode register write commands can be used to load a memory row address or a memory column address into the memory row address registers or the memory column address registers, respectively. During a read operation directed to a second memory row and/or column of the memory array, the circuitry can compare the second memory row to the first memory row and/or the second memory column to the first memory column, and can poison a data bit read from the memory array before the data bit is output from the memory device when the first and second memory row addresses match and/or when the first and second memory column addresses match.

公开(公告)号：US12242724B2

公开(公告)日：2025-03-04

申请号：US17944509

申请日：2022-09-14

Applicant: Micron Technology, Inc.

Inventor： Mow Yiak Goh ,  Mark Clouse

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to conversion of access data based on memory device size are described herein. An example apparatus can include a memory device, a mode register, an address decoder, and a memory controller. The memory device can include an array of memory cells. The memory controller can cause performance of a memory access. Performance of the memory access can include receiving access data associated with a first memory device size to access data stored in the memory device. The memory device can be a second memory device size. Performance of the memory access can further include accessing the data in the memory device that is the second memory device size using the access data.

公开(公告)号：US20240311231A1

公开(公告)日：2024-09-19

申请号：US18525395

申请日：2023-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Wesley W. Borie ,  Dennis G. Montierth ,  Garth N. Grubb ,  Mow Yiak Goh ,  Anthony M. Geidl

IPC: G06F11/10 ,  G06F12/02

CPC classification number: G06F11/10 ,  G06F12/0292 ,  G06F2212/1032

Abstract: An exemplary host includes a data mapping decoder configured to decode a swizzle mapping signal received from a memory module to provide a data mapping setting, a data input/output circuit configured to receive a plurality of data bits from the memory module via a data bus, and a data adjustment circuit configured to re-arrange an order of the plurality of data bits based on the data mapping setting to provide a plurality of adjusted data bits.

公开(公告)号：US20240086067A1

公开(公告)日：2024-03-14

申请号：US17944509

申请日：2022-09-14

Applicant: Micron Technology, Inc.

Inventor： Mow Yiak Goh ,  Mark Clouse

IPC: G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/0659 ,  G06F3/0673

Abstract: Systems, apparatuses, and methods related to conversion of access data based on memory device size are described herein. An example apparatus can include a memory device, a mode register, an address decoder, and a memory controller. The memory device can include an array of memory cells. The memory controller can cause performance of a memory access. Performance of the memory access can include receiving access data associated with a first memory device size to access data stored in the memory device. The memory device can be a second memory device size. Performance of the memory access can further include accessing the data in the memory device that is the second memory device size using the access data.

公开(公告)号：US20240070007A1

公开(公告)日：2024-02-29

申请号：US18223465

申请日：2023-07-18

Applicant: Micron Technology, Inc.

Inventor： Aaron Jannusch ,  Mow Yiak Goh ,  Robin K. Mitra

IPC: G06F11/07

CPC classification number: G06F11/0772

Abstract: Memory with fail indicators, and associated systems, devices, and methods are disclosed herein. In one embodiment, a system includes a plurality of memory systems and a host device. At least one of the memory systems includes a fail indicator connected to the host device via a side channel of the system. The host device is configured to detect an occurrence of a failure on the at least one memory system and to initiate activation of the fail indicator. The side channel can be an I2C or I3C side channel. The fail indicator, when activated, can provide a visual indication of the failure. For example, the fail indicator can include an LED that can be activated to emit light and provide an indication of the failure. A color of the light can correspond to a type, occurrence, or location of the failure on the at least one memory system.

公开(公告)号：US20240311238A1

公开(公告)日：2024-09-19

申请号：US18525354

申请日：2023-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wesley W. Borie ,  Dennis G. Montierth ,  Garth N. Grubb ,  Mow Yiak Goh ,  Anthony M. Geidl

IPC: G06F11/10 ,  G06F11/16 ,  G11C8/08 ,  G11C17/16

CPC classification number: G06F11/1068 ,  G06F11/1654 ,  G11C8/08 ,  G11C17/16

Abstract: An exemplary memory includes a first sub-wordline (SWL) driver configured to provide first data from a memory cell array, a second SWL driver configured to provide second data from a memory cell array, and an input/output (I/O) circuit configured to receive the first data and the second data from the first and second SWL drivers, respectively. The I/O circuit including a data terminal mapping circuit configured to selectively route the first data and the second data to different respective data terminal based on a data terminal mapping setting.

公开(公告)号：US20230214130A1

公开(公告)日：2023-07-06

申请号：US17959131

申请日：2022-10-03

Applicant: Micron Technology, Inc.

Inventor： Joshua E. Alzheimer ,  Mow Yiak Goh ,  Loren J. Wooley

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F3/0673 ,  G06F3/0629 ,  G06F11/1044

Abstract: Memory with address-selectable data poisoning circuitry is disclosed herein. In one embodiment, a memory device comprises circuitry operably connected to a memory array. The circuitry can include memory row address registers and/or memory column address registers. Standard access commands or mode register write commands can be used to load a memory row address or a memory column address into the memory row address registers or the memory column address registers, respectively. During a read operation directed to a second memory row and/or column of the memory array, the circuitry can compare the second memory row to the first memory row and/or the second memory column to the first memory column, and can poison a data bit read from the memory array before the data bit is output from the memory device when the first and second memory row addresses match and/or when the first and second memory column addresses match.