公开(公告)号：US10770466B2

公开(公告)日：2020-09-08

申请号：US16258296

申请日：2019-01-25

Applicant: Micron Technology, Inc.

Inventor： Naoyoshi Kobayashi ,  Osamu Fujita ,  Katsumi Koge

IPC: H01L27/108

Abstract: A semiconductor device comprises laterally-neighboring word lines having respective word line caps thereon, an active region between the laterally-neighboring word lines and word line caps, an insulating material and a semiconductive material adjacent the word line caps, and a digit line contact between opposing substantially vertical surfaces of the semiconductive material, between opposing substantially vertical surfaces of the insulating material, adjacent to substantially horizontal surfaces of the word line caps, and between opposing substantially vertical surfaces of the word line caps. A transition surface extending between and connecting the substantially horizontal surface and the substantially vertical surface of the respective word line caps projects toward a longitudinal axis extending centrally through the digit line contact. Methods of forming the semiconductor device are also disclosed, as are electronic systems including the semiconductor device.

公开(公告)号：US12114490B2

公开(公告)日：2024-10-08

申请号：US17558323

申请日：2021-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Naoyoshi Kobayashi ,  Tsuyoshi Tomoyama

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/488

Abstract: An apparatus includes a substrate; a memory cell region provided over the substrate; a peripheral region provided over the substrate and adjacent to the memory cell region; and a plurality of word-lines extending in parallel across the memory cell region and the peripheral region; a first insulating film covering top surfaces of the plurality of word-lines in each of the memory cell region and the peripheral region and covering side surfaces of upper portions of the plurality of word-lines in the peripheral region without covering side surfaces of the upper portions of the plurality of word-lines in the memory cell region.

公开(公告)号：US20230200058A1

公开(公告)日：2023-06-22

申请号：US17558323

申请日：2021-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Naoyoshi Kobayashi ,  Tsuyoshi Tomoyama

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10891 ,  H01L27/10894

Abstract: An apparatus includes a substrate; a memory cell region provided over the substrate; a peripheral region provided over the substrate and adjacent to the memory cell region; and a plurality of word-lines extending in parallel across the memory cell region and the peripheral region; a first insulating film covering top surfaces of the plurality of word-lines in each of the memory cell region and the peripheral region and covering side surfaces of upper portions of the plurality of word-lines in the peripheral region without covering side surfaces of the upper portions of the plurality of word-lines in the memory cell region.

公开(公告)号：US10546863B1

公开(公告)日：2020-01-28

申请号：US16053505

申请日：2018-08-02

Applicant: Micron Technology, Inc.

Inventor： Naoyoshi Kobayashi

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/3205 ,  H01L23/532 ,  H01L23/528

Abstract: Disclosed herein is a method that includes: forming a composite layer, the composite layer comprising first and second insulative materials and a first polysilicon layer that is between the first and second insulative materials, forming a hole in the composite layer, the hole penetrating through the composite layer to define respective edge portions of the first and second insulative materials and the first polysilicon layer, and converting the edge portion of the first polysilicon layer into third insulative material so that the third insulative material is between the respective edges of the first and second insulative materials.

公开(公告)号：US09960114B1

公开(公告)日：2018-05-01

申请号：US15585396

申请日：2017-05-03

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Andrew L. Li ,  Sanh D. Tang ,  Naoyoshi Kobayashi ,  Katsumi Koge

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76837 ,  H01L27/10814 ,  H01L27/10885

Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.

公开(公告)号：US20200243539A1

公开(公告)日：2020-07-30

申请号：US16258296

申请日：2019-01-25

Applicant: Micron Technology, Inc.

Inventor： Naoyoshi Kobayashi ,  Osamu Fujita ,  Katsumi Koge

IPC: H01L27/108

Abstract: A semiconductor device comprises laterally-neighboring word lines having respective word line caps thereon, an active region between the laterally-neighboring word lines and word line caps, an insulating material and a semiconductive material adjacent the word line caps, and a digit line contact between opposing substantially vertical surfaces of the semiconductive material, between opposing substantially vertical surfaces of the insulating material, adjacent to substantially horizontal surfaces of the word line caps, and between opposing substantially vertical surfaces of the word line caps. A transition surface extending between and connecting the substantially horizontal surface and the substantially vertical surface of the respective word line caps projects toward a longitudinal axis extending centrally through the digit line contact. Methods of forming the semiconductor device are also disclosed, as are electronic systems including the semiconductor device.

公开(公告)号：US10128183B1

公开(公告)日：2018-11-13

申请号：US15926505

申请日：2018-03-20

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Andrew L. Li ,  Sanh D. Tang ,  Naoyoshi Kobayashi ,  Katsumi Koge

IPC: H01L23/522 ,  H01L21/768

Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.

公开(公告)号：US20180323142A1

公开(公告)日：2018-11-08

申请号：US15926505

申请日：2018-03-20

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Andrew L. Li ,  Sanh D. Tang ,  Naoyoshi Kobayashi ,  Katsumi Koge

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76837 ,  H01L23/5222 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10885

Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.