公开(公告)号：US20250021501A1

公开(公告)日：2025-01-16

申请号：US18767645

申请日：2024-07-09

Applicant: Micron Technology, Inc.

Inventor： Jeremy Kuehlwein ,  Neil Petrie ,  Ming-ta Hsieh ,  Gregory A. King

IPC: G06F13/24 ,  H01H1/00 ,  H02H9/04

Abstract: Input/output (I/O) components can include electromechanical switches that can be placed respectively on signal lines coupled between transceivers and I/O pads. Electromechanical switches can operate to isolate respective transceivers from the other transceivers and/or I/O pads to protect those transceivers from ESD events. Electromechanical switches of I/O components can be micro-electromechanical systems (MEMS) switches.

公开(公告)号：US20230395146A1

公开(公告)日：2023-12-07

申请号：US17831414

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Neil Petrie ,  Yoav Weinberg

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C2013/0054 ,  G11C13/0038 ,  G11C13/0069

Abstract: An example apparatus include an array of memory cells. The example apparatus includes a memory controller coupled to the array. The memory controller can include an internal reference resistor. The memory controller can be configured to monitor memory characteristics for the array and the memory controller. The memory controller can be configured to trim the internal reference resistor to result in a target resistance value based on the memory characteristics.

公开(公告)号：US12159667B2

公开(公告)日：2024-12-03

申请号：US17831414

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Neil Petrie ,  Yoav Weinberg

IPC: G11C13/00

Abstract: An example apparatus include an array of memory cells. The example apparatus includes a memory controller coupled to the array. The memory controller can include an internal reference resistor. The memory controller can be configured to monitor memory characteristics for the array and the memory controller. The memory controller can be configured to trim the internal reference resistor to result in a target resistance value based on the memory characteristics.

公开(公告)号：US10153775B1

公开(公告)日：2018-12-11

申请号：US15701689

申请日：2017-09-12

Applicant: Micron Technology, Inc.

Inventor： Steven G. Wurzer ,  Neil Petrie ,  Joseph P. Kerzman ,  Kevin R. Duncan

IPC: H03B28/00 ,  H03L7/099 ,  G11B20/14

Abstract: Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.

公开(公告)号：US10425090B2

公开(公告)日：2019-09-24

申请号：US16043350

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Steven G. Wurzer ,  Neil Petrie ,  Joseph P. Kerzman ,  Kevin R. Duncan

IPC: H03L7/099 ,  H03B28/00 ,  G11B20/14

Abstract: Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.

公开(公告)号：US20190081632A1

公开(公告)日：2019-03-14

申请号：US16043350

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Steven G. Wurzer ,  Neil Petrie ,  Joseph P. Kerzman ,  Kevin R. Duncan

IPC: H03L7/099 ,  G11B20/14

CPC classification number: H03L7/0998 ,  G11B20/1426 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  H03B28/00

Abstract: Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.

公开(公告)号：US20250013589A1

公开(公告)日：2025-01-09

申请号：US18764965

申请日：2024-07-05

Applicant: Micron Technology, Inc.

Inventor： Ming-ta Hsieh ,  Neil Petrie ,  Gregory A. King

IPC: G06F13/20 ,  H01H1/00

Abstract: An interface, such as an input/output expander (IOE), includes microelectromechanical (MEMS) switches that are operable to connect or disconnect respective signal lines on the interface. MEMS switches may be less susceptible to electrostatic discharge (ESD) damages, which eliminates a need for ESD protection circuits for each MEMS switch. The interface can have improved performance due to the eliminated need for the ESD protection circuits, which otherwise may have introduced jitter in signal propagation.