公开(公告)号：US20240320177A1

公开(公告)日：2024-09-26

申请号：US18598791

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Nikesh AGARWAL ,  Robert M. WALKER

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4013 ,  G06F13/4221

Abstract: A system comprising an interface between a host and a device, wherein the interface is configured to reorder messages to package flits to reduce or eliminate underutilized bandwidth in one or both directions of a bidirectional link. In one example, the interface is in accordance with the CXL specification, and the host and the device (e.g., a memory device) include CXL-compliant controllers to pack and unpack flits.

公开(公告)号：US20240320167A1

公开(公告)日：2024-09-26

申请号：US18598722

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Nikesh AGARWAL ,  Robert M. WALKER

IPC: G06F13/16

CPC classification number: G06F13/1668

Abstract: Provided is a system comprising a communication interface between a host and a device, wherein the header of a first memory request transmitted on the forward link of the communication interface encodes, in a bit vector, addresses to be read for a plurality of second memory requests. Combining one or more read requests with another request such that a single request header is transmitted for a plurality of respective requests provides for more efficient use of the forward link bandwidth. Corresponding methods are also described.

公开(公告)号：US20240345982A1

公开(公告)日：2024-10-17

申请号：US18444550

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Nikesh AGARWAL ,  Chandana MANJULA LINGANNA

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4221 ,  G06F13/1642

Abstract: A memory device comprises a plurality of backend interfaces that are each configured to connect to a respective media device (e.g., DDR, LPDDR DRAM), a plurality of reliability, availability and serviceability (RAS) channel datapaths with each RAS channel datapath connected to one or more backend interfaces, one or more caches that are each connected to at least one RAS channel datapath, and control circuitry. The control circuitry is configured to: in response to receiving a memory access request for a memory location, search a cache of the one or more caches for the requested memory location; and when, in response to the search, the requested memory location is not found in the cache, obtain the requested memory location from a media device connected to the at least one RAS channel datapath. Corresponding methods are also described.

公开(公告)号：US20240184477A1

公开(公告)日：2024-06-06

申请号：US18349053

申请日：2023-07-07

Applicant: Micron Technology, Inc.

Inventor： Nikesh AGARWAL

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: In a computer host system, a system and method to compress the transmission between the central processing unit (CPU) and the dynamic random access memory (DRAM) of either of an extended consecutive series of ‘0’ bits or an extended consecutive series of ‘1’ bits. The CPU or a Compute Express Link (CXL) Initiator associated with the CPU identifies the consecutive strings of ‘0’ bits or ‘1’ bits. The CPU or the CXL Initiator sets data flags in a FLIT data structure, using just two bits or four bits to indicate the strings. The data structure is sent to a CXL memory, which interprets the flags and constructs the extended series of ‘0’ bits or extended series of ‘1’ bits.

公开(公告)号：US20240330182A1

公开(公告)日：2024-10-03

申请号：US18444552

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Nikesh AGARWAL ,  Chandana MANJULA LINGANNA

IPC: G06F12/0802

CPC classification number: G06F12/0802

Abstract: A memory device comprises a plurality of backend interfaces that are each configured to connect to a respective media device (e.g., DDR, LPDDR DRAM), a plurality of reliability, availability and serviceability (RAS) channel datapaths with each RAS channel datapath connected to one or more backend interfaces, one or more caches that are each connected to at least one RAS channel datapath, and control circuitry. The control circuitry is configured to: in response to receiving a memory access request for a memory location, search a cache of the one or more caches for the requested memory location; and when, in response to the search, the requested memory location is not found in the cache, obtain the requested memory location from a media device connected to the at least one RAS channel datapath. Corresponding methods are also described.

公开(公告)号：US20240281399A1

公开(公告)日：2024-08-22

申请号：US18444545

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Nikesh AGARWAL ,  Chanda MANJULA LINGANAA

IPC: G06F13/42

CPC classification number: G06F13/4221 ,  G06F2213/0026

Abstract: A method performed by a protocol controller for packing a frame includes selecting, based on current contents of at least one message buffer, a stored packing template, and packing the frame in accordance with the selected packing template. The packing comprises packing each slot of the frame with a respective request (e.g., read request, write request) from the message buffer in accordance with the selected packing template. The template is selected from a plurality of stored packing templates. Associated host devices on which the protocol controller is arranged are also described.