公开(公告)号：US20240176697A1

公开(公告)日：2024-05-30

申请号：US18521600

申请日：2023-11-28

Applicant: Micron Technology, Inc.

Inventor： Smruti Subhash Jhaveri ,  Hyun Yoo Lee

IPC: G06F11/10 ,  G06F13/42

CPC classification number: G06F11/1016 ,  G06F11/1068 ,  G06F13/4221

Abstract: Described apparatuses and methods facilitate sharing redundant memory portions at a controller-level to enable memory repair between two or more memory blocks. Each memory die of multiple memory dies can include, for instance, multiple spare rows for use if a row of a memory array has a faulty bit. If a memory die has more faults than spare rows, the memory die cannot repair the additional faults. This document describes a controller that can inventory unrepaired faults and available spare rows across multiple memory dies. The controller can then “borrow” a spare row from a second memory die that has an available one and “share” the spare row with a first memory die that has a fault than it cannot repair. The controller can remap a memory access request targeting the row with the unrepaired fault in the first memory die to a spare row in the second memory die.

公开(公告)号：US20240371460A1

公开(公告)日：2024-11-07

申请号：US18651357

申请日：2024-04-30

Applicant: Micron Technology, Inc.

Inventor： Smruti Subhash Jhaveri ,  Hyunyoo Lee

IPC: G11C29/56

Abstract: During a command bus training (CBT), interconnected memory dice are accessed in a sequence determined (e.g., predetermined) by a bit sequence generator and via a shared data link for retrieving a respective set of feedback data of the CBT from each memory dice. This eliminates a need to individually train and/or control interconnected memory dice for the CBT; thereby, providing a flexible and scalable architecture that can accommodate a range of memory densities (e.g., a number of memory dice that are interconnected) and making it a valuable solution for high-performance memory applications.

公开(公告)号：US20240070102A1

公开(公告)日：2024-02-29

申请号：US17823423

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Creston M. Dupree ,  Smruti Subhash Jhaveri ,  Hyun Yoo Lee ,  John Christopher Sancon ,  Kang-Yong Kim ,  Francesco Douglas Verna-Ketel

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/1668

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, a controller may train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine, using at least one logical operation, bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

公开(公告)号：US12235784B2

公开(公告)日：2025-02-25

申请号：US17823423

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Creston M. Dupree ,  Smruti Subhash Jhaveri ,  Hyun Yoo Lee ,  John Christopher Sancon ,  Kang-Yong Kim ,  Francesco Douglas Verna-Ketel

IPC: G06F13/40 ,  G06F13/16

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, a controller may train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine, using at least one logical operation, bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

公开(公告)号：US20250021875A1

公开(公告)日：2025-01-16

申请号：US18755355

申请日：2024-06-26

Applicant: Micron Technology, Inc.

Inventor： Wonjun Choi ,  Hyunyoo Lee ,  Smruti Subhash Jhaveri

IPC: G06N20/00

Abstract: Test data associated with a command bus training (CBT) can be separately received at interconnected memory dice. Feedback data that are outputted from the multiple interconnected memory dice in response to the test data can be randomly combined such that combined feedback data is returned as if the feedback data were sent from a single memory die. This provides a flexible and scalable architecture that can accommodate a range of memory densities (e.g., a number of memory dice that are interconnected).

公开(公告)号：US12235783B2

公开(公告)日：2025-02-25

申请号：US17823415

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Francesco Douglas Verna-Ketel ,  Hyun Yoo Lee ,  Smruti Subhash Jhaveri ,  John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim

IPC: G06F13/40 ,  G06F13/16

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

公开(公告)号：US20240170038A1

公开(公告)日：2024-05-23

申请号：US18511404

申请日：2023-11-16

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Smruti Subhash Jhaveri ,  Kang-Yong Kim

IPC: G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/40615

Abstract: Described apparatuses and methods relate to adaptive refresh staggering for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a memory device can include logic that can be programmed to stagger the start of refresh operations for each die upon receiving a command to enter a lower-power mode, such as self-refresh. The staggered start can be implemented at a channel level, a package level, or both. The programming sets a delay for each die so that initiation of refresh operations is staggered. Thus, a first die can initiate refresh operations when a command to enter the lower-power mode is received (e.g., approximately zero delay). However, initiation of refresh operations for subsequent dies (e.g., “after” the first die) is delayed, which can reduce peak current draw and power consumption.

公开(公告)号：US20240070101A1

公开(公告)日：2024-02-29

申请号：US17823415

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Francesco Douglas Verna-Ketel ,  Hyun Yoo Lee ,  Smruti Subhash Jhaveri ,  John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/1668

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.