公开(公告)号：US20240079305A1

公开(公告)日：2024-03-07

申请号：US17930021

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Bong Woo Choi ,  Venkateswarlu Bhavanasi ,  Naga Raju Sykam

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0652 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/45111 ,  H01L2224/45116 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48227

Abstract: An embedded trace substrate assembly includes a build-up lamination material with an upper surface on a die side and a board side. A solder-resist material on the die side defines a bond-wire section where bond-finger pads include a first lateral width top first and second plating materials are on the bond-finger pads. The top second plating material has a top surface that above the upper surface of the build-up lamination material. The wire-bond section includes a row of the bond-finger pads, the top first plating material and the top second plating material, and the solder-resist material is set back from a portion of the upper surface and from the bond-finger pads.

公开(公告)号：US20230290684A1

公开(公告)日：2023-09-14

申请号：US17690981

申请日：2022-03-09

Applicant: Micron Technology, Inc.

Inventor： Wei Chang Wong ,  Radhakrishna Kotti ,  Raj K. Bansal ,  Youngik Kwon ,  Po Chih Yang ,  Venkateswarlu Bhavanasi

IPC: H01L21/78 ,  H01L23/58

CPC classification number: H01L21/78 ,  H01L23/585 ,  H01L27/108

Abstract: Structures and methods for separating semiconductor wafers into individual dies are disclosed. A semiconductor wafer or panel can include a crack assist structure in a scribe junction. The crack assist structure can include a plurality of vertical walls extending at least partially through a thickness of the wafer. In some embodiments, the plurality of vertical walls can be coupled to a weak interface. The weak interface can guide cracks that form during the dicing process in a direction along the walls, away from active circuitry. After dicing, the resulting semiconductor devices can include a plurality of vertical walls extending at least partially through a thickness of the semiconductor device. Each of the plurality of vertical walls can include at least a portion extending substantially parallel to a sidewall of the semiconductor device.

公开(公告)号：US20240071975A1

公开(公告)日：2024-02-29

申请号：US17899522

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Bong Woo Choi ,  Venkateswarlu Bhavanasi ,  Wen How Sim ,  Harjashan Veer Singh

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26165 ,  H01L2224/27005 ,  H01L2224/27515 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/1431 ,  H01L2924/1438 ,  H01L2924/35121

Abstract: Substrates with spacers, including substrates with solder resist spacers, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate comprises a first surface, a solder resist layer disposed over at least a portion of the first surface, and a plurality of electrical contacts at the first surface of the substrate. Electrical contacts of the plurality are configured to be coupled to corresponding electrical contacts at a surface of an electronic device. The substrate further includes a solder resist spacer disposed on the solder resist layer. The solder resist spacer can have a height corresponding to a thickness of the electronic device. The solder resist spacer can be configured as a dam to limit bleed out of underfill laterally away from the plurality of electrical contacts along the first surface and toward the solder resist spacer.

公开(公告)号：US20230395419A1

公开(公告)日：2023-12-07

申请号：US17805013

申请日：2022-06-01

Applicant: Micron Technology, Inc

Inventor： Ankur Harish Shah ,  Venkateswarlu Bhavanasi ,  Wen How Sim ,  Harjashan Veer Singh

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/67

CPC classification number: H01L21/6836 ,  H01L21/7806 ,  H01L21/67132 ,  H01L2221/68327 ,  H01L2221/68386

Abstract: Methods of identifying damaged microelectronic devices are described. A method includes applying a detection material to an active surface of a wafer. The detection material includes an additive configured to yield a visible reaction to heat or infrared or near-infrared light. The method may further include focusing a laser beam into an interior portion of the wafer through a second surface of the wafer opposite the active surface to form a modified layer along a separation region extending between adjacent microelectronic devices. The method may also include inspecting the detection material for visible reactions. The method may further include identifying reactions that indicate exposure to heat or infrared or near-infrared light over a pre-determined threshold. Protective tape, backgrind tapes, and methods of manufacturing a microelectronic device are also described.