公开(公告)号：US20240079358A1

公开(公告)日：2024-03-07

申请号：US17939880

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Siva Sai Kishore Palli ,  Venkata Rama Satya Pradeep Vempaty ,  Wen How Sim ,  Chen Yu Huang ,  Harjashan Veer Singh

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05573 ,  H01L2224/16014 ,  H01L2224/1607 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06593 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/384

Abstract: Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate and a die stack carried by the package substrate. The die stack can include at least a first semiconductor die carried by the package substrate, a second semiconductor die carried by the first semiconductor die. The first semiconductor die can have an upper surface and a first bond pad carried by the upper surface that includes a curvilinear concave depression formed in an uppermost surface of the first bond pad. The second semiconductor die has a lower surface and a second bond pad carried by the lower surface. The die stack can also include solder structure electrically coupling the first and second bond pads and at least partially filling the curvilinear concave depression formed in the uppermost surface of the first bond pad.

公开(公告)号：US20250154378A1

公开(公告)日：2025-05-15

申请号：US18926872

申请日：2024-10-25

Applicant: Micron Technology, Inc.

Inventor： Ankur Harish Shah ,  Wen How Sim ,  Harjashan Veer Singh

IPC: C09J5/06 ,  H01L23/00

Abstract: Die attach adhesives with tailorable characteristics using selectively releasable additives (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a die attach adhesive includes (i) a primary material composition or resin and (ii) a structure within the primary material composition or resin. The die attach adhesive can further include one or more additives (a) contained within the structure and/or (b) mixed with the primary material composition or resin. The structure can be configured to release the one or more additives in response to a stimulus applied to the die attach adhesive. In some embodiments, the die attach adhesive can be a die attach film. In these and other embodiments, the structure can be a nanosphere. Additionally, or alternatively, the one or more additives can include a crosslink modifier, a viscosity modifier, and/or an anti-electrostatic discharge additive.

公开(公告)号：US20240071975A1

公开(公告)日：2024-02-29

申请号：US17899522

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Bong Woo Choi ,  Venkateswarlu Bhavanasi ,  Wen How Sim ,  Harjashan Veer Singh

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26165 ,  H01L2224/27005 ,  H01L2224/27515 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/1431 ,  H01L2924/1438 ,  H01L2924/35121

Abstract: Substrates with spacers, including substrates with solder resist spacers, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate comprises a first surface, a solder resist layer disposed over at least a portion of the first surface, and a plurality of electrical contacts at the first surface of the substrate. Electrical contacts of the plurality are configured to be coupled to corresponding electrical contacts at a surface of an electronic device. The substrate further includes a solder resist spacer disposed on the solder resist layer. The solder resist spacer can have a height corresponding to a thickness of the electronic device. The solder resist spacer can be configured as a dam to limit bleed out of underfill laterally away from the plurality of electrical contacts along the first surface and toward the solder resist spacer.

公开(公告)号：US20230395419A1

公开(公告)日：2023-12-07

申请号：US17805013

申请日：2022-06-01

Applicant: Micron Technology, Inc

Inventor： Ankur Harish Shah ,  Venkateswarlu Bhavanasi ,  Wen How Sim ,  Harjashan Veer Singh

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/67

CPC classification number: H01L21/6836 ,  H01L21/7806 ,  H01L21/67132 ,  H01L2221/68327 ,  H01L2221/68386

Abstract: Methods of identifying damaged microelectronic devices are described. A method includes applying a detection material to an active surface of a wafer. The detection material includes an additive configured to yield a visible reaction to heat or infrared or near-infrared light. The method may further include focusing a laser beam into an interior portion of the wafer through a second surface of the wafer opposite the active surface to form a modified layer along a separation region extending between adjacent microelectronic devices. The method may also include inspecting the detection material for visible reactions. The method may further include identifying reactions that indicate exposure to heat or infrared or near-infrared light over a pre-determined threshold. Protective tape, backgrind tapes, and methods of manufacturing a microelectronic device are also described.