公开(公告)号：US10790303B2

公开(公告)日：2020-09-29

申请号：US16793560

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Woohee Kim ,  John D. Hopkins ,  Changhan Kim

IPC: H01L21/28 ,  H01L21/02 ,  H01L27/11582 ,  H01L29/10 ,  H01L27/1157 ,  H01L29/423

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels include conductive wordline material having terminal ends. Charge blocking material is along the terminal ends of the conductive wordline material and has first vertical faces. The insulative levels have terminal ends with second vertical faces. The second vertical faces are laterally offset relative to the first vertical faces. Charge-trapping material is along the first vertical faces, and extends partially along the second vertical faces. The charge-trapping material is configured as segments which are vertically spaced from one another by gaps. Charge-tunneling material extends along the segments of the charge-trapping material. Channel material extends vertically along the stack, and is spaced from the charge-trapping material by the charge-tunneling material. The channel material extends into the gaps. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10319586B1

公开(公告)日：2019-06-11

申请号：US15860388

申请日：2018-01-02

Applicant: Micron Technology, Inc.

Inventor： John A. Smythe ,  Woohee Kim ,  Stefan Uhlenbrock

IPC: C23C16/34 ,  C23C16/40 ,  C23C16/46 ,  H01L21/02 ,  C23C16/455

CPC classification number: H01L21/0228 ,  C23C16/345 ,  C23C16/401 ,  C23C16/45527 ,  C23C16/46 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02172

Abstract: An example method comprises an ALD sequence including contacting an outer substrate surface at a temperature T1 with a first precursor to form a monolayer onto the outer substrate surface. Temperature of the outer substrate surface and the monolayer thereon is increased to a temperature T2 that is at least 200° C. greater than a maximum of the temperature T1. The temperature-increasing is at a temperature-increasing rate that takes no more than 10 seconds to get the outer substrate surface and the monolayer thereon at least 200° C. above the maximum temperature T1. At the temperature T2, the monolayer is contacted with a second precursor that reacts with the monolayer to form a reaction product and a new outer substrate surface that each comprise a component from the monolayer and a component from the second precursor. With the monolayer not having been allowed to be at least 200° C. above the maximum temperature T1 for more than 10 seconds, temperature of the new outer substrate surface is decreased from the temperature T2 to a lower temperature TL that is at least 200° C. lower than a minimum of the temperature T2.

公开(公告)号：US20200185413A1

公开(公告)日：2020-06-11

申请号：US16793560

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Woohee Kim ,  John D. Hopkins ,  Changhan Kim

IPC: H01L27/11582 ,  H01L21/28 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L27/1157

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels include conductive wordline material having terminal ends. Charge blocking material is along the terminal ends of the conductive wordline material and has first vertical faces. The insulative levels have terminal ends with second vertical faces. The second vertical faces are laterally offset relative to the first vertical faces. Charge-trapping material is along the first vertical faces, and extends partially along the second vertical faces. The charge-trapping material is configured as segments which are vertically spaced from one another by gaps. Charge-tunneling material extends along the segments of the charge-trapping material. Channel material extends vertically along the stack, and is spaced from the charge-trapping material by the charge-tunneling material. The channel material extends into the gaps. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20180219021A1

公开(公告)日：2018-08-02

申请号：US15422335

申请日：2017-02-01

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/10 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/4234

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20180323212A1

公开(公告)日：2018-11-08

申请号：US16031919

申请日：2018-07-10

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/10

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L29/1037 ,  H01L29/4234 ,  H01L29/7926

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US10083981B2

公开(公告)日：2018-09-25

申请号：US15422335

申请日：2017-02-01

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L21/28 ,  H01L29/10

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US10593695B1

公开(公告)日：2020-03-17

申请号：US16162672

申请日：2018-10-17

Applicant: Micron Technology, Inc.

Inventor： Woohee Kim ,  John D. Hopkins ,  Changhan Kim

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L29/10 ,  H01L21/02 ,  H01L29/423 ,  H01L21/28

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels include conductive wordline material having terminal ends. Charge blocking material is along the terminal ends of the conductive wordline material and has first vertical faces. The insulative levels have terminal ends with second vertical faces. The second vertical faces are laterally offset relative to the first vertical faces. Charge-trapping material is along the first vertical faces, and extends partially along the second vertical faces. The charge-trapping material is configured as segments which are vertically spaced from one another by gaps. Charge-tunneling material extends along the segments of the charge-trapping material. Channel material extends vertically along the stack, and is spaced from the charge-trapping material by the charge-tunneling material. The channel material extends into the gaps. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10541252B2

公开(公告)日：2020-01-21

申请号：US16410973

申请日：2019-05-13

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L21/28 ,  H01L29/10 ,  H01L29/792

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20190267396A1

公开(公告)日：2019-08-29

申请号：US16410973

申请日：2019-05-13

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L29/10 ,  H01L21/28 ,  H01L29/792 ,  H01L29/423

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20190206674A1

公开(公告)日：2019-07-04

申请号：US15860388

申请日：2018-01-02

Applicant: Micron Technology, Inc.

Inventor： John A. Smythe ,  Woohee Kim ,  Stefan Uhlenbrock

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/46 ,  C23C16/40 ,  C23C16/34

CPC classification number: H01L21/0228 ,  C23C16/345 ,  C23C16/401 ,  C23C16/45527 ,  C23C16/46 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02172

Abstract: An example method comprises an ALD sequence including contacting an outer substrate surface at a temperature T1 with a first precursor to form a monolayer onto the outer substrate surface. Temperature of the outer substrate surface and the monolayer thereon is increased to a temperature T2 that is at least 200° C. greater than a maximum of the temperature T1. The temperature-increasing is at a temperature-increasing rate that takes no more than 10 seconds to get the outer substrate surface and the monolayer thereon at least 200° C. above the maximum temperature T1. At the temperature T2, the monolayer is contacted with a second precursor that reacts with the monolayer to form a reaction product and a new outer substrate surface that each comprise a component from the monolayer and a component from the second precursor. With the monolayer not having been allowed to be at least 200° C. above the maximum temperature T1 for more than 10 seconds, temperature of the new outer substrate surface is decreased from the temperature T2 to a lower temperature TL that is at least 200° C. lower than a minimum of the temperature T2.