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1.发明授权Track and hold amplifiers and digital calibration for analog-to-digital converters 有权跟踪和保持放大器和模数转换器的数字校准公开(公告)号：US08350738B2
公开(公告)日：2013-01-08
申请号：US13010285
申请日：2011-01-20
IPC分类号： H03M1/10
CPC分类号： G11C27/02 , H03M1/1061 , H03M1/365
摘要： An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices. Each of the slices in turn includes a differential preamplifier coupled to the track-and-hold amplifier and to a corresponding location on the voltage ladder; a current mode logic latch comparator coupled to the differential preamplifier; a large-swing latch coupled to the current mode logic latch comparator; a complementary metal oxide semiconductor latch having a dummy load; a calibration digital to analog converter connected across outputs of the differential preamplifier to inject calibration currents; and a register coupled to the calibration digital to analog converter and storing calibration values for use thereby. The analog-to-digital converter also includes a multiplexer which multiplexes outputs of the complementary metal oxide semiconductor latches down to a predetermined number of outputs.
摘要翻译： 示例性的差分跟踪和保持放大器包括轨道平台，该轨道平台包括在其各自的输入处并联并联的第一和第二线性化对，并且在它们各自的输出处并联。 差分跟踪和保持放大器还包括选择性地耦合到第一和第二线性化对的输出的保持级。 保持级包括具有反馈的单位增益缓冲器，其具有在其输出端互连的保持电容器。 差分跟踪和保持放大器还包括耦合到保持级的输出的输出缓冲器。 示例性模数转换器包括差分跟踪保持放大器，电压梯和多个片。 每个切片依次包括耦合到跟踪保持放大器和电压梯上相应位置的差分前置放大器; 耦合到差分前置放大器的电流模式逻辑锁存比较器; 耦合到电流模式逻辑锁存比较器的大摆动锁存器; 具有虚拟负载的互补金属氧化物半导体锁存器; 连接在差分前置放大器的输出端的校准数模转换器，以注入校准电流; 以及耦合到校准数模转换器的寄存器，并存储用于其的校准值。 模数转换器还包括多路复用器，其将互补金属氧化物半导体锁存器的输出多路复用到预定数量的输出。
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2.发明申请Track and Hold Amplifiers and Digital Calibration for Analog-to-Digital Converters 有权跟踪和保持放大器和模数转换器的数字校准公开(公告)号：US20120188109A1
公开(公告)日：2012-07-26
申请号：US13010285
申请日：2011-01-20
CPC分类号： G11C27/02 , H03M1/1061 , H03M1/365
摘要： An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices. Each of the slices in turn includes a differential preamplifier coupled to the track-and-hold amplifier and to a corresponding location on the voltage ladder; a current mode logic latch comparator coupled to the differential preamplifier; a large-swing latch coupled to the current mode logic latch comparator; a complementary metal oxide semiconductor latch having a dummy load; a calibration digital to analog converter connected across outputs of the differential preamplifier to inject calibration currents; and a register coupled to the calibration digital to analog converter and storing calibration values for use thereby. The analog-to-digital converter also includes a multiplexer which multiplexes outputs of the complementary metal oxide semiconductor latches down to a predetermined number of outputs.
摘要翻译： 示例性的差分跟踪和保持放大器包括轨道平台，该轨道平台包括在其各自的输入处并联并联的第一和第二线性化对，并且在它们各自的输出处并联。 差分跟踪和保持放大器还包括选择性地耦合到第一和第二线性化对的输出的保持级。 保持级包括具有反馈的单位增益缓冲器，其具有在其输出端互连的保持电容器。 差分跟踪和保持放大器还包括耦合到保持级的输出的输出缓冲器。 示例性模数转换器包括差分跟踪保持放大器，电压梯和多个片。 每个切片依次包括耦合到跟踪保持放大器和电压梯上相应位置的差分前置放大器; 耦合到差分前置放大器的电流模式逻辑锁存比较器; 耦合到电流模式逻辑锁存比较器的大摆动锁存器; 具有虚拟负载的互补金属氧化物半导体锁存器; 连接在差分前置放大器的输出端的校准数模转换器，以注入校准电流; 以及耦合到校准数模转换器的寄存器，并存储用于其的校准值。 模数转换器还包括多路复用器，其将互补金属氧化物半导体锁存器的输出多路复用到预定数量的输出。
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3.发明申请OPTIMAL DITHERING OF A DIGITALLY CONTROLLED OSCILLATOR WITH CLOCK DITHERING FOR GAIN AND BANDWIDTH CONTROL 有权数字控制振荡器的最佳抖动，具有时钟抖动，用于增益和带宽控制公开(公告)号：US20100188158A1
公开(公告)日：2010-07-29
申请号：US12358736
申请日：2009-01-23
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/099
摘要： A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.
摘要翻译： 数字锁相环（DPLL）和方法包括可调延迟线，其配置为接收参考时钟作为输入并输出抖动参考时钟信号。 相位和频率检测器（PFD）被配置为将抖动参考时钟信号与反馈时钟信号进行比较，以确定抖动参考时钟信号和反馈时钟信号之间的相位和频率差。 数字控制振荡器（DCO）被配置为接收来自PFD的早期或晚期确定以根据其调整输出，其中抖动参考时钟信号分配抖动响应以增强DPLL的整体操作。
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4.发明授权Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control 有权具有时钟抖动的数字控制振荡器的最佳抖动，用于增益和带宽控制公开(公告)号：US08138840B2
公开(公告)日：2012-03-20
申请号：US12358736
申请日：2009-01-23
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
摘要： A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.
摘要翻译： 数字锁相环（DPLL）和方法包括可调延迟线，其配置为接收参考时钟作为输入并输出抖动参考时钟信号。 相位和频率检测器（PFD）被配置为将抖动参考时钟信号与反馈时钟信号进行比较，以确定抖动参考时钟信号和反馈时钟信号之间的相位和频率差。 数字控制振荡器（DCO）被配置为接收来自PFD的早期或晚期确定以根据其调整输出，其中抖动参考时钟信号分配抖动响应以增强DPLL的整体操作。
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5.发明授权公开(公告)号：US08294525B2
公开(公告)日：2012-10-23
申请号：US12818790
申请日：2010-06-18
申请人： John Francis Bulzacchelli , Zeynep Toprak Deniz , Daniel Joseph Friedman , Shahrzad Naraghi , Alexander V Rylyakov
发明人： John Francis Bulzacchelli , Zeynep Toprak Deniz , Daniel Joseph Friedman , Shahrzad Naraghi , Alexander V Rylyakov
IPC分类号： H03L7/085
CPC分类号： H03L7/0995 , H03M1/0612 , H03M1/14 , H03M1/502 , H03M1/60
摘要： Apparatuses and methods are provided relating to a voltage controlled oscillator (VCO) based on current starved inverting delay stages; wherein in each stage a PMOS transistor as header and an NMOS transistor as footer are used with their gate-to-source voltages always equal to analog control voltage. The analog control voltage is also used as the supply voltage of the oscillator. An exemplary apparatus includes a VCO of n stages, where n is an odd number and where each stage includes a current starved inverter where the analog control voltage is also used as the supply voltage of each delay stage.
摘要翻译： 提供了关于基于当前饥饿的反相延迟级的压控振荡器（VCO）的装置和方法; 其中在每个阶段中，使用PMOS晶体管作为集管和作为栅极的NMOS晶体管，其栅极至源极电压总是等于模拟控制电压。 模拟控制电压也用作振荡器的电源电压。 示例性装置包括n级的VCO，其中n是奇数，并且其中每级包括当前饥饿逆变器，其中模拟控制电压也用作每个延迟级的电源电压。
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