公开(公告)号：US08294525B2

公开(公告)日：2012-10-23

申请号：US12818790

申请日：2010-06-18

申请人： John Francis Bulzacchelli ,  Zeynep Toprak Deniz ,  Daniel Joseph Friedman ,  Shahrzad Naraghi ,  Alexander V Rylyakov

发明人： John Francis Bulzacchelli ,  Zeynep Toprak Deniz ,  Daniel Joseph Friedman ,  Shahrzad Naraghi ,  Alexander V Rylyakov

IPC分类号： H03L7/085

CPC分类号： H03L7/0995 ,  H03M1/0612 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60

摘要： Apparatuses and methods are provided relating to a voltage controlled oscillator (VCO) based on current starved inverting delay stages; wherein in each stage a PMOS transistor as header and an NMOS transistor as footer are used with their gate-to-source voltages always equal to analog control voltage. The analog control voltage is also used as the supply voltage of the oscillator. An exemplary apparatus includes a VCO of n stages, where n is an odd number and where each stage includes a current starved inverter where the analog control voltage is also used as the supply voltage of each delay stage.

摘要翻译： 提供了关于基于当前饥饿的反相延迟级的压控振荡器（VCO）的装置和方法; 其中在每个阶段中，使用PMOS晶体管作为集管和​​作为栅极的NMOS晶体管，其栅极至源极电压总是等于模拟控制电压。 模拟控制电压也用作振荡器的电源电压。 示例性装置包括n级的VCO，其中n是奇数，并且其中每级包括当前饥饿逆变器，其中模拟控制电压也用作每个延迟级的电源电压。

公开(公告)号：US20080107212A1

公开(公告)日：2008-05-08

申请号：US11557695

申请日：2006-11-08

申请人： Steven John Baumgartner ,  Anthony Richard Bonaccio ,  John Francis Bulzacchelli ,  Daniel Mark Dreps

发明人： Steven John Baumgartner ,  Anthony Richard Bonaccio ,  John Francis Bulzacchelli ,  Daniel Mark Dreps

IPC分类号： H03D1/00

CPC分类号： H03H11/02

摘要： A method for implementing phase rotator circuits and phase rotator circuit of the invention includes a polyphase filter network to create a quadrature phase version of the input signal. The polyphase filter network is partitioned into a first part that is physically isolated from the phase rotator circuit and a second part that is embedded in the phase rotator circuit. The second part of the polyphase filter is coupled to the first part of the polyphase filter by a high-pass equalizing buffer stage. The second part of the polyphase filter is coupled to the phase rotator circuit by a bandlimiting buffer stage.

摘要翻译： 用于实现本发明的相位旋转电路和相位旋转电路的方法包括多相滤波器网络，以产生输入信号的正交相位版本。 多相滤波器网络被划分为与相位旋转电路物理隔离的第一部分和嵌入在相位旋转电路中的第二部分。 多相滤波器的第二部分通过高通均衡缓冲级耦合到多相滤波器的第一部分。 多相滤波器的第二部分通过带限幅缓冲器级耦合到相位旋转器电路。

公开(公告)号：US08126045B2

公开(公告)日：2012-02-28

申请号：US12201487

申请日：2008-08-29

申请人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

发明人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

IPC分类号： H03H7/40

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03617

摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexers is clock-gated for isolation of subsequent ciruitry from the outputs of the sense amplifiers during a precharged period. A gating circuit is configured to perform gating of a selected signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.

摘要翻译： 决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。 检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。 通道门复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟门控的，用于在预充电时段期间从读出放大器的输出隔离后续电路。 选通电路被配置为利用时钟信号来执行从第二电路部分输出的选定信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。 再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。

公开(公告)号：US07792185B2

公开(公告)日：2010-09-07

申请号：US11672309

申请日：2007-02-07

申请人： John Francis Bulzacchelli ,  Matthew J. Park

发明人： John Francis Bulzacchelli ,  Matthew J. Park

IPC分类号： H03H7/30

CPC分类号： G06G7/18 ,  H03K5/02

摘要： Methods and apparatus are disclosed for calibrating summing amplifiers based on current integration. For example, apparatus for calibrating output voltage levels of a current-integrating summing amplifier includes the following components. A duplicate integrator circuit is provided, wherein the duplicate integrator circuit replicates an integrator circuit of the current-integrating summing amplifier. A comparing circuit, coupled to the duplicate integrator circuit, is provided for comparing at least one output voltage level generated by the duplicate integrator circuit with a reference voltage level. A feedback loop circuit, coupled to the comparing circuit and the duplicate integrator circuit, is provided for adjusting at least one bias signal of the duplicate integrator circuit so that the output voltage level generated by the duplicate integrator circuit matches the reference voltage level, wherein the bias signal is applied to the integrator circuit of the current-integrating summing amplifier thereby calibrating output signal components due to multiple input signals of the current-integrating summing amplifier.

摘要翻译： 公开了基于当前积分校准加法放大器的方法和装置。 例如，用于校准电流积分求和放大器的输出电压电平的装置包括以下部件。 提供了一种重复的积分器电路，其中双重积分电路复合了积分积分放大器的积分电路。 提供耦合到重复积分器电路的比较电路，用于将由双重积分器电路产生的至少一个输出电压电平与参考电压电平进行比较。 提供耦合到比较电路和双重积分电路的反馈环路电路，用于调整复合积分电路的至少一个偏置信号，使得由双重积分电路产生的输出电压电平与参考电压电平相匹配，其中， 偏置信号被施加到电流积分求和放大器的积分器电路，从而由于积分求和放大器的多个输入信号而校准输出信号分量。

公开(公告)号：US07733984B2

公开(公告)日：2010-06-08

申请号：US11557695

申请日：2006-11-08

申请人： Steven John Baumgartner ,  Anthony Richard Bonaccio ,  John Francis Bulzacchelli ,  Daniel Mark Dreps

发明人： Steven John Baumgartner ,  Anthony Richard Bonaccio ,  John Francis Bulzacchelli ,  Daniel Mark Dreps

IPC分类号： H04L27/00

CPC分类号： H03H11/02

摘要： A method for implementing phase rotator circuits and phase rotator circuit of the invention includes a polyphase filter network to create a quadrature phase version of the input signal. The polyphase filter network is partitioned into a first part that is physically isolated from the phase rotator circuit and a second part that is embedded in the phase rotator circuit. The second part of the polyphase filter is coupled to the first part of the polyphase filter by a high-pass equalizing buffer stage. The second part of the polyphase filter is coupled to the phase rotator circuit by a bandlimiting buffer stage.

摘要翻译： 用于实现本发明的相位旋转电路和相位旋转电路的方法包括多相滤波器网络，以产生输入信号的正交相位版本。 多相滤波器网络被划分为与相位旋转电路物理隔离的第一部分和嵌入在相位旋转电路中的第二部分。 多相滤波器的第二部分通过高通均衡缓冲级耦合到多相滤波器的第一部分。 多相滤波器的第二部分通过带限幅缓冲器级耦合到相位旋转器电路。

公开(公告)号：US20080187037A1

公开(公告)日：2008-08-07

申请号：US11672309

申请日：2007-02-07

申请人： John Francis Bulzacchelli ,  Matthew J. Park

发明人： John Francis Bulzacchelli ,  Matthew J. Park

IPC分类号： H03K5/159 ,  G06G7/18 ,  G05F1/10

CPC分类号： G06G7/18 ,  H03K5/02

摘要： Methods and apparatus are disclosed for calibrating summing amplifiers based on current integration. For example, apparatus for calibrating output voltage levels of a current-integrating summing amplifier includes the following components. A duplicate integrator circuit is provided, wherein the duplicate integrator circuit replicates an integrator circuit of the current-integrating summing amplifier. A comparing circuit, coupled to the duplicate integrator circuit, is provided for comparing at least one output voltage level generated by the duplicate integrator circuit with a reference voltage level. A feedback loop circuit, coupled to the comparing circuit and the duplicate integrator circuit, is provided for adjusting at least one bias signal of the duplicate integrator circuit so that the output voltage level generated by the duplicate integrator circuit matches the reference voltage level, wherein the bias signal is applied to the integrator circuit of the current-integrating summing amplifier thereby calibrating output signal components due to multiple input signals of the current-integrating summing amplifier.

摘要翻译： 公开了基于当前积分校准加法放大器的方法和装置。 例如，用于校准电流积分求和放大器的输出电压电平的装置包括以下部件。 提供了一种重复的积分器电路，其中双重积分电路复合了积分积分放大器的积分电路。 提供耦合到重复积分器电路的比较电路，用于将由双重积分器电路产生的至少一个输出电压电平与参考电压电平进行比较。 提供耦合到比较电路和双重积分电路的反馈环路电路，用于调整复合积分电路的至少一个偏置信号，使得由双重积分电路产生的输出电压电平与参考电压电平相匹配，其中， 偏置信号被施加到电流积分求和放大器的积分器电路，从而由于积分求和放大器的多个输入信号而校准输出信号分量。

公开(公告)号：US20100054324A1

公开(公告)日：2010-03-04

申请号：US12201487

申请日：2008-08-29

申请人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

发明人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

IPC分类号： H03H7/40

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03617

摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexer is clock-gated for isolation of subsequent circuitry from the outputs of the sense amplifiers during a precharge period. A gating circuit is configured to perform gating of a select signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.

摘要翻译： 决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。 检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。 门控多路复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟选通的，用于在预充电期间将后续电路与读出放大器的输出隔离。 选通电路被配置为利用时钟信号来执行从第二电路部分输出的选择信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。 再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。