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公开(公告)号：US5982449A
公开(公告)日：1999-11-09
申请号：US780253
申请日：1997-01-08
申请人： Miho Nagai , Takashi Yamaguchi , Yutaka Nio , Hideto Nakahigashi , Hideyo Uwabata , Toshiaki Kitahara , Chikara Gotanda , Atsushi Ishizu
发明人： Miho Nagai , Takashi Yamaguchi , Yutaka Nio , Hideto Nakahigashi , Hideyo Uwabata , Toshiaki Kitahara , Chikara Gotanda , Atsushi Ishizu
摘要： A television receiver comprising an information extracting circuit for extracting information from a format or content of an input video signal, a video signal processing circuit for processing this video signal by a program or data, a memory for storing the program and data, a CPU for controlling, operating or driving these elements, and a display device for displaying an image. The video signal processing circuit can, under the control of the CPU, decode the signal, correct or set the picture quality such as gradation and sharpness, or adaptively process an on-screen display based on the input video signal. The television receiver is also able to adaptively extend the functions of the television receiver corresponding to various signal formats.
摘要翻译： 一种电视接收机，包括：用于从输入视频信号的格式或内容中提取信息的信息提取电路，用于通过程序或数据处理该视频信号的视频信号处理电路，用于存储程序和数据的存储器，用于存储程序和数据的存储器 控制，操作或驱动这些元件，以及用于显示图像的显示装置。 视频信号处理电路可以在CPU的控制下对信号进行解码，校正或设置诸如灰度和清晰度的图像质量，或者基于输入视频信号自适应地处理屏幕显示。 电视接收机还能够自适应地扩展对应于各种信号格式的电视接收机的功能。
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公开(公告)号：US06704056B2
公开(公告)日：2004-03-09
申请号：US09861587
申请日：2001-05-22
IPC分类号： H04N510
摘要： A video signal conversion part of a horizontal deflection circuit deletes a prescribed number of horizontal scanning lines from a vertical blanking interval of an input video signal and assigns a time corresponding to the deleted horizontal scanning lines to horizontal blanking intervals of the remaining horizontal scanning lines thereby extending the horizontal blanking interval of each horizontal scanning line and outputting a video signal. A synchronizing signal separation circuit extracts a horizontal synchronizing signal and a vertical synchronizing signal from the video signal output from the video signal conversion part. An output part of the horizontal deflection circuit supplies a sawtooth horizontal deflection current to a horizontal deflection yoke in synchronization with the horizontal synchronizing signal output from the synchronizing signal separation circuit.
摘要翻译： 水平偏转电路的视频信号转换部分从输入视频信号的垂直消隐间隔中删除规定数量的水平扫描线，并将与删除的水平扫描线对应的时间分配给其余水平扫描线的水平消隐间隔，由此 延长每条水平扫描线的水平消隐间隔并输出视频信号。 同步信号分离电路从视频信号转换部分输出的视频信号中提取水平同步信号和垂直同步信号。 水平偏转电路的输出部分与从同步信号分离电路输出的水平同步信号同步地向水平偏转线圈提供锯齿水平偏转电流。
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3.发明授权Interpolation apparatus, and video signal processing apparatus including the same 失效插值装置和包括其的视频信号处理装置公开(公告)号：US06795123B2
公开(公告)日：2004-09-21
申请号：US10028545
申请日：2001-12-19
IPC分类号： H04N701
CPC分类号： H04N7/0135 , H04N7/012
摘要： An interpolation apparatus that generates interpolation pixel values necessary for converting input video data of interlace scanning into video data of progressive scanning is provided. A plurality of candidate pixel-pairs each of which is composed of two pixels that are symmetric with respected to a pixel that is going to be interpolated are selected from pixels on adjacent two scan lines within one field of the input video data, and a difference between pixel values of each selected pixel-pair is calculated. A pixel-pair to be used for generating the interpolation pixel value is determined, based on the smallest difference and the second smallest difference of the calculated differences. An interpolation pixel value of the pixel that is going to be interpolated is generated based on pixel values of the determined pixel-pair.
摘要翻译： 提供了一种内插装置，其生成将隔行扫描的输入视频数据转换为逐行扫描的视频数据所需的内插像素值。 从输入视频数据的一个场内的相邻的两条扫描线上的像素中选择多个候选像素对，每个候选像素对由相对于要插值的像素对称的两个像素组成，并且差异 计算每个所选像素对的像素值之间。 基于计算出的差的最小差和第二最小差，确定用于生成内插像素值的像素对。 基于所确定的像素对的像素值来生成将被内插的像素的内插像素值。
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公开(公告)号：US07596188B2
公开(公告)日：2009-09-29
申请号：US10548066
申请日：2004-05-27
申请人： Chikara Gotanda , Yutaka Nio , Kouichiro Nagata
发明人： Chikara Gotanda , Yutaka Nio , Kouichiro Nagata
IPC分类号： H03K9/00
CPC分类号： H04N7/52 , H04N5/08 , H04N5/4401 , H04N5/46 , H04N5/63 , H04N21/43632 , H04N21/4436
摘要： A power-down determination circuit calculates the horizontal frequency and vertical frequency, respectively, employing a clock signal obtained from a multiplier circuit and horizontal synchronization signal and vertical synchronization signal obtained from a TMDS decode circuit. The power-down determination circuit then determines whether an input digital signal does or does not have a decodable video format by comparing the calculated horizontal frequency and vertical frequency with horizontal frequencies and vertical frequencies stored beforehand, for output of a power-down control signal indicative of the determination. Thus, in the case where the input digital signal does not have a decodable format, the power-down control signal controls a video/audio processing circuit to enter a power-down mode.
摘要翻译： 断电确定电路分别使用从乘法电路获得的时钟信号和从TMDS解码电路获得的水平同步信号和垂直同步信号来计算水平频率和垂直频率。 断电确定电路然后通过将计算的水平频率和垂直频率与预先存储的水平频率和垂直频率进行比较来确定输入数字信号是否具有可解码的视频格式，用于输出指示的掉电控制信号 的决心。 因此，在输入数字信号不具有可解码格式的情况下，掉电控制信号控制视频/音频处理电路进入掉电模式。
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公开(公告)号：US20060077298A1
公开(公告)日：2006-04-13
申请号：US10548066
申请日：2004-05-27
申请人： Chikara Gotanda , Yutaka Nio , Kouichiro Nagata
发明人： Chikara Gotanda , Yutaka Nio , Kouichiro Nagata
IPC分类号： H04N3/27
CPC分类号： H04N7/52 , H04N5/08 , H04N5/4401 , H04N5/46 , H04N5/63 , H04N21/43632 , H04N21/4436
摘要： A power-down determination circuit calculates the horizontal frequency and vertical frequency, respectively, employing a clock signal obtained from a multiplier circuit and horizontal synchronization signal and vertical synchronization signal obtained from a TMDS decode circuit. The power-down determination circuit then determines whether an input digital signal does or does not have a decodable video format by comparing the calculated horizontal frequency and vertical frequency with horizontal frequencies and vertical frequencies stored beforehand, for output of a power-down control signal indicative of the determination. Thus, in the case where the input digital signal does not have a decodable format, the power-down control signal controls a video/audio processing circuit to enter a power-down mode.
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6.发明授权Memory controller for controlling an integrated memory undergoing logical state transitions 失效用于控制正在进行逻辑状态转换的集成存储器的存储器控制器公开(公告)号：US06678832B1
公开(公告)日：2004-01-13
申请号：US09430538
申请日：1999-10-29
申请人： Chikara Gotanda
发明人： Chikara Gotanda
IPC分类号： G06F132
CPC分类号： H04N5/63 , G06F13/1689 , H04N5/44 , H04N21/4305 , H04N21/4436 , Y02D10/14
摘要： A controller and a control method of an integrated memory provided in a system LSI used in television receiver or other video appliance are disclosed. In the memory controller of the invention, when a clock signal suspend command signal not synchronized with a synchronization signal is entered, a suspend command signal synchronized with the synchronization signal is generated. The clock signal supplied in the integrated memory is suspended according to a synchronized suspend command signal. Since the clock signal supply is suspended only while the integrated memory is in idling state, the power consumption of the system LSI can be saved without breaking down the integrated memory.
摘要翻译： 公开了一种在电视接收机或其他视频设备中使用的系统LSI中提供的集成存储器的控制器和控制方法。 在本发明的存储器控制器中，当输入与同步信号不同步的时钟信号暂停指令信号时，产生与同步信号同步的暂停指令信号。 根据同步的挂起指令信号暂停在集成存储器中提供的时钟信号。 由于仅在集成存储器处于空闲状态时暂停时钟信号供给，因此可以节省系统LSI的功耗，而不会破坏集成存储器。
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公开(公告)号：US20150002624A1
公开(公告)日：2015-01-01
申请号：US14372907
申请日：2012-01-20
申请人： Haruko Terai , Chikara Gotanda , Ryuichi Shibutani
发明人： Haruko Terai , Chikara Gotanda , Ryuichi Shibutani
IPC分类号： H04N13/00
CPC分类号： H04N13/139 , G06T3/4007 , H04N2013/0088
摘要： A video signal processing device includes: an extraction unit which extracts, from each frame of an input video including a right-eye image and a left-eye image, one of the right-eye image and the left-eye image as an extracted image; and an image enlargement processing unit which (i) forms an interpolated image by enlarging the extracted image extracted by the extraction unit, through pixel interpolation using a pixel included in a previous frame, and (ii) outputs the interpolated image, the previous frame being a frame previous to the frame including the extracted image.
摘要翻译： 视频信号处理装置包括：提取单元，从包括右眼图像和左眼图像的输入视频的每帧中提取右眼图像和左眼图像中的一个作为提取图像 ; 以及图像放大处理单元，其通过使用包括在前一帧中的像素的像素插值来扩大由所述提取单元提取的所提取的图像来形成内插图像，以及（ii）输出所述内插图像，所述前一帧为 包括提取的图像的帧之前的帧。
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公开(公告)号：US20110187708A1
公开(公告)日：2011-08-04
申请号：US12995200
申请日：2010-04-20
IPC分类号： G06T15/00
CPC分类号： H04N5/44504 , H04N5/44508 , H04N13/111 , H04N13/183 , H04N21/4882 , H04N21/4886 , H04N21/814
摘要： An image processor includes a 3D image output section for outputting a 3D image; an average parallax calculator for calculating a parallax level of each predetermined pixel based on a lefty-eye image and a right-eye image, and calculating an average screen parallax level based on the parallax level; a data acquisition section for detecting the type of 3D image or a characteristic of synthesized image; a correcting and synthesizing section for correcting the average screen parallax level depending on the type of 3D image or the characteristic of synthesized image, setting a corrected average parallax level as parallax to be added to the caption or OSD, adding the parallax to the caption or OSD, and synthesizing a caption or OSD with parallax; and an image synthesizer for superimposing the caption or OSD synthesized image with parallax on the 3D image.
摘要翻译： 图像处理器包括用于输出3D图像的3D图像输出部分; 平均视差计算器，用于基于左眼图像和右眼图像计算每个预定像素的视差水平，并且基于视差水平计算平均屏幕视差水平; 用于检测3D图像的类型或合成图像的特性的数据获取部分; 校正和合成部分，用于根据3D图像的类型或合成图像的特性校正平均屏幕视差水平，将校正的平均视差水平设置为要添加到字幕或OSD的视差，将视差加到标题或 OSD，并且合成具有视差的字幕或OSD; 以及用于将字幕或OSD合成图像与视差叠加在3D图像上的图像合成器。
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