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11 条记录 (耗时 0.022 秒)

    Clock generating circuit
    1.
    发明授权
    Clock generating circuit 失效
    时钟发生电路

    公开(公告)号：US06781431B2

    公开(公告)日：2004-08-24

    申请号：US10349033

    申请日：2003-01-23

    申请人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Okamoto

    发明人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Okamoto

    IPC分类号： G06F104

    CPC分类号： H03K3/0315 ,  H02M3/07 ,  H03K3/013 ,  H03K3/70

    摘要： The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.

    摘要翻译： 用于产生时钟信号的时钟发生电路包括具有以环形配置连接的奇数个反相器的环形振荡器。 当激活信号处于第一电平时，环形振荡器被激活以产生时钟信号，并且当激活信号处于第二电平时被停止产生时钟信号。 锁存电路连接到环形振荡器的输出节点，并且响应于激活信号从第一电平到第二电平的转变而保持环形振荡器的输出节点的电平。 当激活信号从H电平降低到L电平时，锁存时钟信号的电平，从而防止产生时钟信号中的毛刺。

    Semiconductor memory provided with data-line equalizing circuit
    4.
    发明授权
    Semiconductor memory provided with data-line equalizing circuit 失效
    半导体存储器配有数据线均衡电路

    公开(公告)号：US06373763B1

    公开(公告)日：2002-04-16

    申请号：US09839403

    申请日：2001-04-23

    申请人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mako Okamoto

    发明人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mako Okamoto

    IPC分类号： G11C700

    CPC分类号： G11C7/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094

    摘要： An equalizing circuit includes a plurality of N-channel MOS transistors for respectively setting a data line to a predetermined precharge voltage. The H-level voltage Vddb of a control signal for turning on these N-channel MOS transistors is set to a range higher than the sum of the precharge voltage and a transistor threshold voltage. A Vddb generation circuit steps up an external power-supply voltage and sets a voltage Vddb in a range lower than a step-up voltage for activating a word line.

    摘要翻译： 均衡电路包括用于分别将数据线设置为预定预充电电压的多个N沟道MOS晶体管。 用于接通这些N沟道MOS晶体管的控制信号的H电平电压Vddb被设置为高于预充电电压和晶体管阈值电压之和的范围。 Vddb生成电路升高外部电源电压，并将电压Vddb设置在低于用于激活字线的升压电压的范围内。

    Semiconductor memory device including internal power circuit having tuning function
    7.
    发明授权
    Semiconductor memory device including internal power circuit having tuning function 失效
    半导体存储器件包括具有调谐功能的内部电源电路

    公开(公告)号：US06665217B2

    公开(公告)日：2003-12-16

    申请号：US10120575

    申请日：2002-04-12

    申请人： Fukashi Morishita ,  Yasuhiko Taito ,  Akira Yamazaki ,  Mako Okamoto ,  Nobuyuki Fujii

    发明人： Fukashi Morishita ,  Yasuhiko Taito ,  Akira Yamazaki ,  Mako Okamoto ,  Nobuyuki Fujii

    IPC分类号： G11C700

    CPC分类号： G11C5/025 ,  G11C5/147

    摘要： A tuning control circuit includes fuse devices each shifting from a conductive state to an interrupted state in response to a program input from the outside, and signal driving circuits for driving the signal levels of tuning control signals in accordance with the states of the fuse devices. A reference voltage generating circuit generates a reference voltage corresponding to a reference value of a memory array voltage of a semiconductor memory device according to the invention in accordance with an electrical resistance value which is finely adjusted in response to the tuning control signals.

    摘要翻译： 调谐控制电路包括响应于来自外部的程序输入而从导通状态转换到中断状态的熔丝器件，以及根据保险丝器件的状态来驱动调谐控制信号的信号电平的信号驱动电路。 参考电压产生电路根据根据本发明的半导体存储器件的存储器阵列电压的参考值产生与根据调谐控制信号精细调节的电阻值相对应的参考电压。

    Semiconductor device provided with potential transmission line
    8.
    发明授权
    Semiconductor device provided with potential transmission line 失效
    设置有潜在传输线的半导体器件

    公开(公告)号：US06593642B2

    公开(公告)日：2003-07-15

    申请号：US09987257

    申请日：2001-11-14

    申请人： Mako Okamoto ,  Yasuhiko Taito ,  Fukashi Morishita ,  Akira Yamazaki ,  Nobuyuki Fujii

    发明人： Mako Okamoto ,  Yasuhiko Taito ,  Fukashi Morishita ,  Akira Yamazaki ,  Nobuyuki Fujii

    IPC分类号： G01F110

    CPC分类号： H01L27/10897 ,  G11C11/4074 ,  H01L27/0218

    摘要： A DRAM is provided at a portion relating to generation of a boosted potential with a filter circuit located between a detector circuit and a ring oscillator for removing a pulse-like change in level from an output signal of the detector circuit. Accordingly, temporary stop of the charge pump circuit can be prevented even when the boosted potential exceeds in a pulse-like manner the reference potential at the vicinity of the output node of the charge pump circuit, and the boosted potential can be rapidly restored to the reference potential.

    摘要翻译： 在与产生升压电位有关的部分中提供DRAM，该滤波电路位于检测器电路和环形振荡器之间，用于从检测器电路的输出信号中去除脉冲状的电平变化。 因此，即使当升压电位以类似脉冲的方式超过电荷泵电路的输出节点附近的基准电位时，也可以防止电荷泵电路的暂时停止，并且可以将升压电位迅速恢复到 参考潜力。

    Semiconductor memory device with internal power supply potential generation circuit
    9.
    发明授权
    Semiconductor memory device with internal power supply potential generation circuit 失效
    具有内部电源电位生成电路的半导体存储器件

    公开(公告)号：US06424579B1

    公开(公告)日：2002-07-23

    申请号：US09827897

    申请日：2001-04-09

    申请人： Mihoko Akiyama ,  Akira Yamazaki ,  Fukashi Morishita ,  Yasuhiko Taito ,  Nobuyuki Fujii ,  Mako Okamoto

    发明人： Mihoko Akiyama ,  Akira Yamazaki ,  Fukashi Morishita ,  Yasuhiko Taito ,  Nobuyuki Fujii ,  Mako Okamoto

    IPC分类号： G11C700

    CPC分类号： G11C5/147

    摘要： In an eDRAM, there are provided a VDC that down-converts an external power supply potential to generate an internal power supply potential for a sense amplifier band, and a VDC that down-converts the external power supply potential to generate an internal power supply potential for a column decoder. The response of the VDC is improved by increasing the through current of the VDC only during the period of time corresponding to an amplify operation of the sense amplifier. Therefore, current consumption is smaller than the conventional case where the through current of the VDC is set at a high constant level.

    摘要翻译： 在eDRAM中，提供了一个VDC，其降低转换外部电源电位以产生用于读出放大器频带的内部电源电位;以及VDC，其降低转换外部电源电位以产生内部电源电位 用于列解码器。 通过仅在对应于读出放大器的放大操作的时间段期间增加VDC的通过电流来提高VDC的响应。 因此，电流消耗小于将VDC的通电电流设定为高恒定电平的常规情况。

    Semiconductor device including detector circuit capable of performing high-speed operation
    10.
    发明授权
    Semiconductor device including detector circuit capable of performing high-speed operation 有权
    包括能够执行高速操作的检测器电路的半导体装置

    公开(公告)号：US07479820B2

    公开(公告)日：2009-01-20

    申请号：US11272798

    申请日：2005-11-15

    申请人： Mako Okamoto ,  Fukashi Morishita

    发明人： Mako Okamoto ,  Fukashi Morishita

    IPC分类号： G05F3/02

    CPC分类号： G11C5/145 ,  G11C11/4074 ,  G11C11/4085 ,  H03K5/2481

    摘要： A detector circuit and a negative voltage generating circuit capable of performing high-speed operation are provided. A negative voltage generating circuit includes a charge pump circuit, a first voltage divider circuit that makes a voltage division between an output of the charge pump circuit and a power supply to output a detect potential, a reference voltage generating circuit that generates a reference potential, and a comparator circuit that compares the detect potential and the reference potential. The charge pump circuit is driven by an output signal of the comparator circuit and generates the negative voltage. In the first voltage divider circuit, NMOS transistors and make the voltage division between the negative voltage and the power supply to obtain the detect potential.

    摘要翻译： 提供能够执行高速操作的检测器电路和负电压产生电路。 负电压产生电路包括电荷泵电路，在电荷泵电路的输出和电源之间进行分压以输出检测电位的第一分压电路，产生参考电位的基准电压产生电路， 以及比较电路，其比较检测电位和参考电位。 电荷泵电路由比较器电路的输出信号驱动，并产生负电压。 在第一分压电路中，NMOS晶体管和负电压和电源之间的分压获得检测电位。