公开(公告)号：US5302921A

公开(公告)日：1994-04-12

申请号：US869767

申请日：1992-04-16

申请人： Mikio Shigemori ,  Toru Oida ,  Shigeru Hirasawa ,  Katsumi Yamamura

发明人： Mikio Shigemori ,  Toru Oida ,  Shigeru Hirasawa ,  Katsumi Yamamura

IPC分类号： H03B5/32 ,  H03B1/04 ,  H03B5/36 ,  H03L5/00

CPC分类号： H03B5/36 ,  H03B1/04 ,  H03L5/00 ,  H03B2200/007 ,  H03B2202/04 ,  H03B2202/05 ,  H03B2202/084

摘要： A piezoelectric oscillator in which radiation of higher harmonic components is reduced. A piezoelectric vibrator and a semiconductor device are provided in an oscillation circuit for making the piezoelectric vibrator oscillate, as is a filter for cutting components in a predetermined frequency band or higher harmonic components of an oscillation signal outputted from the semiconductor device. The piezoelectric vibrator, the semiconductor device and the filter are packed in one package. Radiation of the higher harmonic components is reduced by placing the filter close to the oscillator, by providing a shielding or by operating portions of the oscillator output circuit with a reduced supply voltage.

摘要翻译： 一种压电振荡器，其中降低了高次谐波分量的辐射。 压电振动器和半导体装置设置在用于使压电振动器振荡的振荡电路中，以及用于切割预定频带中的分量的滤波器或从半导体器件输出的振荡信号的较高谐波分量。 压电振动器，半导体器件和滤波器被包装在一个封装中。 通过将滤波器靠近振荡器，通过提供屏蔽或通过以较低的电源电压来操作振荡器输出电路的部分来降低高次谐波分量的辐射。

公开(公告)号：USRE36973E

公开(公告)日：2000-11-28

申请号：US837217

申请日：1997-04-22

申请人： Mikio Shigemori

发明人： Mikio Shigemori

IPC分类号： H03L1/02 ,  H04B1/40 ,  H04B1/10

CPC分类号： H04B1/40 ,  H03L1/026

摘要： A radio transceiver having digitally-corrected temperature-compensated crystal oscillators (DTCXOs) including digital frequency temperature compensation circuits that are temporarily suspended from being updated, such that temperature compensation updates that can generate noise during periods of reception and transmission that could interfere with the audio channel and/or signal synchronization will be postponed. Temperature is converted to a digital signal that is then used to address a PROM. The PROM outputs a correction word appropriate for the temperature reading and inputs this to a latch. A timing control loads the latch after data has settled. The latched correction word is connected to a bank of switches and capacitors that trim the frequency of the crystal oscillator. During radio transmission and/or reception, the latch will be suspended from loading any new correction words. The last valid correction word, however, will remain.

摘要翻译： 一种具有经数字校正的温度补偿晶体振荡器（DTCXO）的无线电收发器，其包括临时停止更新的数字频率温度补偿电路，使得在接收和传输期间可能产生噪声的温度补偿更新可能会干扰音频 频道和/或信号同步将被推迟。 温度转换为数字信号，然后用于寻址PROM。 PROM输出适合于温度读数的校正字，并将其输入到锁存器。 定时控制在数据确定后加载锁存器。 锁存的校正字连接到一组可以调节晶体振荡器频率的开关和电容器。 在无线电传输和/或接收期间，锁存器将被暂停装载任何新的校正字。 然而，最后一个有效的修正词将保留。

公开(公告)号：US5696950A

公开(公告)日：1997-12-09

申请号：US221680

申请日：1994-03-31

申请人： Kazushige Ichinose ,  Masayuki Kikushima ,  Hideo Karasawa ,  Tooru Shirotori ,  Mikio Shigemori

发明人： Kazushige Ichinose ,  Masayuki Kikushima ,  Hideo Karasawa ,  Tooru Shirotori ,  Mikio Shigemori

IPC分类号： G06F1/08

CPC分类号： H01L24/49 ,  G06F1/08 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12035 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011

摘要： A flexible clock and reset signal generation and distribution system and method for distributing a relatively low frequency clock signal to various elements of a computer system that require higher frequency clock signals for operation and includes programmable frequency synthesizers containing phase locked loop (PLL) type frequency multipliers, which are located physically adjacent to the computer system elements for receiving the low frequency clock signal and generating the various required higher frequency clock signals. The source of the relatively low frequency clock signal is a real-time clock (RTC) module having a crystal oscillator, a reset signal generator, and a low voltage detector. The RTC module switches off the low frequency clock signal when the main system power supply falls below a prescribed voltage level, such as, a battery voltage, or a voltage reference, or a combination battery voltage and voltage reference. Further, the RTC module provides a system reset signal that is asserted a predetermined delay time after the low frequency clock signal is provided.

摘要翻译： 一种灵活的时钟和复位信号发生和分配系统和方法，用于将相对低频的时钟信号分配到需要更高频率时钟信号进行操作的计算机系统的各种元件，并且包括包含锁相环（PLL）型频率乘法器的可编程频率合成器 其物理地邻近计算机系统元件，用于接收低频时钟信号并产生各种所需的较高频率时钟信号。 相对低频时钟信号的源是具有晶体振荡器，复位信号发生器和低电压检测器的实时时钟（RTC）模块。 当主系统电源低于规定的电压电平（例如电池电压或电压基准）或组合电池电压和电压基准时，RTC模块关闭低频时钟信号。 此外，RTC模块提供在提供低频时钟信号之后被断言预定延迟时间的系统复位信号。

公开(公告)号：US07541849B2

公开(公告)日：2009-06-02

申请号：US11463032

申请日：2006-08-08

申请人： Mikio Shigemori ,  Masataka Nomura

发明人： Mikio Shigemori ,  Masataka Nomura

IPC分类号： H03L7/06

CPC分类号： H03L7/18

摘要： A phase locked circuit includes a locked loop circuit having a phase comparator, a voltage controlled oscillator, and a variable frequency divider which divides a clock signal fvco output from the voltage controlled oscillator by n and outputs it. Additionally, the phase locked circuit includes a band pass filter part which is coupled to an output side of the voltage controlled oscillator via a switching part. A frequency division ratio setting signal to be input into the variable frequency divider is input as a switching signal into the switching part so as to switch a frequency of the clock signal fvco output from the voltage controlled oscillator. As synchronizing with switching of the frequency, the switching part switches a plurality of band pass filters provided to the band pass filter part and couples to the voltage controlled oscillator.

摘要翻译： 锁相电路包括具有相位比较器，压控振荡器和可变分频器的锁定环路电路，该可分频器将从压控振荡器输出的时钟信号fvco分频为n并将其输出。 此外，锁相电路包括带通滤波器部分，其经由开关部分耦合到压控振荡器的输出侧。 输入到可变分频器的分频比设置信号作为开关信号输入到开关部分，以便切换从压控振荡器输出的时钟信号fvco的频率。 与频率切换同步，开关部分切换提供给带通滤波器部分的多个带通滤波器并耦合到压控振荡器。

公开(公告)号：US6154095A

公开(公告)日：2000-11-28

申请号：US171812

申请日：1999-01-21

申请人： Mikio Shigemori ,  Hideo Karasawa ,  Toshihiko Kano ,  Kazushige Ichinose

发明人： Mikio Shigemori ,  Hideo Karasawa ,  Toshihiko Kano ,  Kazushige Ichinose

IPC分类号： H03K3/03 ,  H03L7/183 ,  H03B5/32 ,  H03L7/18

CPC分类号： H03L7/183 ,  H03K3/0307 ,  H03J2200/10

摘要： An oscillator circuit having a first programmable divider for obtaining a reference signal by dividing the frequency of an oscillation signal of a piezoelectric resonator by a frequency dividing number M. A PLL circuit using the reference signal as input thereto to obtain a multiplied signal, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number N for a second programmable divider provided in a feedback circuit. A third programmable divider capable of dividing the frequency of the multiplied signal by a third frequency dividing number X and outputting the frequency-divided signal. The frequency dividing numbers M, N, and X can be set to values independent of each other. Therefore, innumerable combinations of the frequency dividing numbers M, N, and X can be used and the number of frequencies producible by one oscillator can be largely increased by enabling selection of any suitable one of such combinations.

摘要翻译： PCT No.PCT / JP98 / 00700 Sec。 371日期1999年1月21日 102（e）日期1999年1月21日PCT提交1998年2月18日PCT公布。 公开号WO98 / 38744 日期1998年9月3日具有第一可编程分频器的振荡器电路，用于通过将压电谐振器的振荡信号的频率除以分频数M来获得参考信号。使用参考信号作为输入的PLL电路获得 相乘的信号通过将输入信号乘以第二分频数N形成，用于设置在反馈电路中的第二可编程分频器。 第三可编程分频器，其能够将乘法信号的频率除以第三分频数X，并输出分频信号。 分频数M，N和X可以被设置为彼此独立的值。 因此，可以使用分频数M，N和X的无数组合，并且可以通过能够选择任何合适的这种组合来大大增加由一个振荡器产生的频率的数量。

公开(公告)号：US5204975A

公开(公告)日：1993-04-20

申请号：US596172

申请日：1990-10-10

申请人： Mikio Shigemori

发明人： Mikio Shigemori

IPC分类号： H03L1/02 ,  H04B1/10 ,  H04B1/40

CPC分类号： H04B1/40 ,  H03L1/026 ,  H04B1/10 ,  H03J2200/10 ,  H03L1/028

摘要： A radio transceiver having digitally-corrected temperature-compensated crystal oscillators (DTCXOs) including digital frequency temperature compensation circuits that are temporarily suspended from being updated, such that temperature compensation updates that can generate noise during periods of reception and transmission that could interfere with the audio channel and/or signal synchronization will be postponed. Temperature is converted to a digital signal that is then used to address a PROM. The PROM outputs a correction word appropriate for the temperature reading and inputs this to a latch. A timing control loads the latch after data has settled. The latched correction word is connected to a bank of switches and capacitors that trim the frequency of the crystal oscillator. During radio transmission and/or reception, the latch will be suspended from loading any new correction words. The last valid correction word, however, will remain.

摘要翻译： 一种具有经数字校正的温度补偿晶体振荡器（DTCXO）的无线电收发器，其包括临时停止更新的数字频率温度补偿电路，使得在接收和传输期间可能产生噪声的温度补偿更新可能会干扰音频 频道和/或信号同步将被推迟。 温度转换为数字信号，然后用于寻址PROM。 PROM输出适合于温度读数的校正字，并将其输入到锁存器。 定时控制在数据确定后加载锁存器。 锁存的校正字连接到一组可以调节晶体振荡器频率的开关和电容器。 在无线电传输和/或接收期间，锁存器将被暂停装载任何新的校正字。 然而，最后一个有效的修正词将保留。

公开(公告)号：US07432770B2

公开(公告)日：2008-10-07

申请号：US11463078

申请日：2006-08-08

申请人： Mikio Shigemori ,  Masataka Nomura

发明人： Mikio Shigemori ,  Masataka Nomura

IPC分类号： H04L7/00

CPC分类号： H04L7/0008 ,  G06F1/12

摘要： The present invention provides a signal transmission device in which jitter occurring in a clock signal is eliminated. The signal transmission device has a construction in which a transmission end IC chip provided with a transmission part of a data signal and a reception end IC chip provided with a reception part of the data signal, the transmission part and the reception part are connected via a data signal transmission line, an oscillator that outputs a clock signal to the transmission part is connected with the transmission end IC chip, a clock signal transmission line is provided which leads the clock signal output from the oscillator to the reception part, and a SAW filter is arranged in the clock signal transmission line.

摘要翻译： 本发明提供了消除在时钟信号中发生抖动的信号传输装置。 该信号传输装置具有以下结构：设置有数据信号的发送部分的发送端IC芯片和设置有数据信号的接收部分的接收端IC芯片，发送部分和接收部分经由 数据信号传输线，向传输部分输出时钟信号的振荡器与发送端IC芯片连接，提供时钟信号传输线，其将从振荡器输出的时钟信号引导到接收部分，并且SAW滤波器 布置在时钟信号传输线中。

公开(公告)号：US06337600B1

公开(公告)日：2002-01-08

申请号：US09671479

申请日：2000-09-27

申请人： Mikio Shigemori ,  Hideo Karasawa ,  Toshihiko Kano ,  Kazushige Ichinose

发明人： Mikio Shigemori ,  Hideo Karasawa ,  Toshihiko Kano ,  Kazushige Ichinose

IPC分类号： H03B532

CPC分类号： H03L7/183 ,  H03J2200/10 ,  H03K3/0307

摘要： An oscillator circuit having a first programmable divider for obtaining a reference signal by dividing the frequency of an oscillation signal of a piezoelectric resonator by a frequency dividing number, M. A PLL circuit using the reference signal as input thereto to obtain a multiplied signal, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number N for a second programmable divider provided in a feedback circuit. A third programmable divider capable of dividing the frequency of the multiplied signal by a third frequency dividing number X and outputting the frequency-divided signal. The frequency dividing numbers M, N, and X can be set to values independent of each other. Therefore, innumerable combinations of the frequency dividing numbers M, N, and X can be used and the number of frequencies producible by one oscillator can be largely increased by enabling selection of any suitable one of such combinations.

摘要翻译： 一种具有第一可编程分频器的振荡器电路，用于通过将压电谐振器的振荡信号的频率除以分频数M来获得参考信号。使用参考信号作为输入的PLL电路以获得相乘的信号， 相乘信号通过将输入信号乘以设置在反馈电路中的第二可编程分频器的第二分频数N而形成。 第三可编程分频器，其能够将乘法信号的频率除以第三分频数X，并输出分频信号。 分频数M，N和X可以被设置为彼此独立的值。 因此，可以使用分频数M，N和X的无数组合，并且可以通过能够选择任何合适的这种组合来大大增加由一个振荡器产生的频率的数量。

公开(公告)号：US6081164A

公开(公告)日：2000-06-27

申请号：US930861

申请日：1997-10-07

申请人： Mikio Shigemori ,  Hideo Karasawa

发明人： Mikio Shigemori ,  Hideo Karasawa

IPC分类号： G06F1/08 ,  H01L23/495 ,  H03L1/02 ,  H03L7/183 ,  H01L23/50 ,  H01L25/16 ,  H03L7/18

CPC分类号： H01L24/06 ,  G06F1/08 ,  H01L23/49596 ,  H01L24/49 ,  H03L1/023 ,  H03L7/183 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12034 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H03J2200/10

摘要： A PLL (phase locked loop) oscillator suitable as a clock signal source for use in a computer system or the like includes a piezoelectric resonator, an oscillating circuit for generating an oscillating signal in cooperation with the piezoelectric resonator, and a PLL circuit which operates using the oscillating signal generated by the oscillating circuit as a reference signal, all these elements being housed in a package, the frequency of the output signal of the PLL oscillator being determined by the oscillation frequency of the oscillating circuit and the frequency dividing ratio of a programmable frequency divider in the PLL circuit, wherein the frequency dividing ratio of the programmable frequency divider is set by writing the data representing the frequency dividing ratio into a programmable read only memory thereby setting the output frequency to a desired value.

摘要翻译： PCT No.PCT / JP97 / 00019 Sec。 371日期1997年10月7日第 102（e）日期1997年10月7日PCT 1997年1月9日PCT PCT。 第WO98 / 31104号公报 日期：1998年7月16日适用于计算机系统等的时钟信号源的PLL（锁相环）振荡器包括压电谐振器，与压电谐振器配合产生振荡信号的振荡电路，以及 使用由振荡电路产生的振荡信号作为参考信号进行工作的PLL电路，将所有这些元件封装在封装中，PLL振荡器的输出信号的频率由振荡电路的振荡频率和频率 PLL电路中的可编程分频器的分频比，其中通过将表示分频比的数据写入可编程只读存储器来设置可编程分频器的分频比，从而将输出频率设置为期望值。