公开(公告)号：US20050140537A1

公开(公告)日：2005-06-30

申请号：US10749571

申请日：2003-12-31

Applicant: Mikko Waltari

Inventor： Mikko Waltari

IPC: H03M1/12 ,  H03M1/34 ,  H03M1/46

CPC classification number: H03M1/1245 ,  H03M1/466

Abstract: An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing unit includes an MDAC with a switched capacitor topology and a sub-ADC. The ADC processing unit is clocked by an internal clock that is N times faster than the sample-and-hold clock. Each cycle is further sub-divided into two phases. During one phase the capacitors are coupled to a residue or sampled voltage provided by the MDAC, and during another phase the capacitor are coupled to a reference voltage determined by the switch control signals generated by the sub-ADC. A set of data bits is generated by the ADC processing unit during each ADC clock cycle. The N sets of data bits are added to generate the digital output stream.

Abstract translation: 算法模数转换器（ADC）包括采样保持电路和并行运行并共享单个运算放大器的ADC处理单元。 ADC处理单元包括具有开关电容拓扑和子ADC的MDAC。 ADC处理单元由比采样和保持时钟快N倍的内部时钟提供时钟。 每个周期进一步细分为两个阶段。 在一个阶段期间，电容器耦合到由MDAC提供的残留或采样电压，并且在另一阶段期间，电容器被耦合到由子ADC产生的开关控制信号确定的参考电压。 ADC处理单元在每个ADC时钟周期内产生一组数据位。 添加N组数据位以产生数字输出流。

公开(公告)号：US20130069812A1

公开(公告)日：2013-03-21

申请号：US13603495

申请日：2012-09-05

Applicant: Mikko Waltari

Inventor： Mikko Waltari

IPC: H03M1/50

CPC classification number: H03M1/0626 ,  H03M1/0836 ,  H03M1/1215 ,  H03M1/1245

Abstract: Processing a signal by receiving an analog input signal located outside of a first Nyquist zone that is between 0 and fs/2; passing the analog input signal through an M-channel time-interleaved analog-to-digital converter (TI-ADC) to generate a TI-ADC output signal; and estimating and correcting a timing skew error in the TI-ADC output signal. Alternatively, an electronic circuit that includes an input for an analog input signal, an M-channel time-interleaved analog-to-digital converter (TI-ADC) and a timing skew error estimating and correcting circuitry. The analog input signal is located outside of a first Nyquist zone that is between 0 and fs/2. The TI-ADC receives the analog input signal and generates a TI-ADC output signal. The timing skew error estimating and correcting circuitry estimates and corrects a timing skew error in the TI-ADC output signal.

Abstract translation: 通过接收位于第一奈奎斯特区之外的位于0和fs / 2之间的模拟输入信号来处理信号; 通过M通道时间交织的模数转换器（TI-ADC）传递模拟输入信号，以产生TI-ADC输出信号; 并估计和校正TI-ADC输出信号中的定时偏移误差。 或者，包括用于模拟输入信号的输入端，M通道时间交替模数转换器（TI-ADC）和定时偏移误差估计和校正电路的电子电路。 模拟输入信号位于0和fs / 2之间的第一奈奎斯特区之外。 TI-ADC接收模拟输入信号并产生TI-ADC输出信号。 定时偏移误差估计和校正电路估计和校正TI-ADC输出信号中的定时偏移误差。

公开(公告)号：US07737875B2

公开(公告)日：2010-06-15

申请号：US12270609

申请日：2008-11-13

Applicant: Mikko Waltari ,  Costantino Pala

Inventor： Mikko Waltari ,  Costantino Pala

IPC: H03M1/34 ,  H03M1/50

CPC classification number: H03M1/206 ,  H03M1/1061 ,  H03M1/362 ,  H03M1/365 ,  H03M1/50

Abstract: An input signal is compared to 2N−1 reference voltages to generate 2N−1 corresponding binary valued comparison signals, delaying at least one of the comparison signals by a variable delay and detecting a difference in arrival time between the delayed signal and another comparison signal. A time interpolation signal encoding a plurality of bins within a least significant bit quantization level is generated, based on the detected difference in arrival time. An M-bit output data is generated based on the comparison signals and the time interpolation signal. A non-uniformity of a code density of the M-bit output data is detected, and based on the detecting the delaying is varied.

Abstract translation: 将输入信号与2N-1个参考电压进行比较以产生2N-1个对应的二进制值比较信号，延迟比较信号中的至少一个可变延迟并检测延迟信号与另一个比较信号之间的到达时间差。 基于检测到的到达时间的差异，生成对最低有效位量化级内的多个存储体进行编码的时间插值信号。 基于比较信号和时间插值信号生成M位输出数据。 检测到M位输出数据的密度不均匀，并且基于检测延迟变化。

公开(公告)号：US07301379B1

公开(公告)日：2007-11-27

申请号：US11194085

申请日：2005-07-29

Applicant: Efram E. Burlingame ,  Mikko Waltari

Inventor： Efram E. Burlingame ,  Mikko Waltari

IPC: H03L7/06

CPC classification number: H03L7/0812

Abstract: A DLL comprises detection circuitry configured to detect a too_slow and a too_fast operating state and correction circuitry configured to correct operation of the DLL when a too_fast or too_slow state is detected. The correction circuitry can be configured to swallow a pulse of the input clock signal when a too_fast condition is detected. The correction circuitry can also be configured to force the DLL into a too_fast operation state, when a too_slow operation state is detected. The correction circuitry can then also be configured to swallow a pulse of the input clock signal once the DLL is in the too_fast operation state.

Abstract translation: DLL包括被配置为检测太低和太快的操作状态的检测电路，以及被配置为当检测到too_fast或too_slow状态时校正DLL的操作的校正电路。 校正电路可以被配置为在检测到too -fast状态时吞咽输入时钟信号的脉冲。 当检测到太低的操作状态时，校正电路也可以被配置成强制DLL进入too_fast操作状态。 然后，一旦DLL处于too_fast操作状态，校正电路也可以被配置成吞入输入时钟信号的脉冲。

公开(公告)号：US20050140536A1

公开(公告)日：2005-06-30

申请号：US10749570

申请日：2003-12-31

Applicant: Mikko Waltari

Inventor： Mikko Waltari

IPC: H03M1/14 ,  H03M1/34

CPC classification number: H03M1/144

Abstract: An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing unit includes an MDAC with a switched capacitor topology and a sub-ADC. The ADC processing unit is clocked by an internal clock that is N times faster than the sample-and-hold clock. Each cycle is further sub-divided into two phases. During one phase the capacitors are coupled to a residue or sampled voltage provided by the MDAC, and during another phase the capacitor are coupled to a reference voltage determined by the switch control signals generated by the sub-ADC. A set of data bits is generated by the ADC processing unit during each ADC clock cycle. The N sets of data bits are added to generate the digital output stream. The internal clock, in turn, has a variable period allocating more time to the early operation phases where more accuracy is required and less time to the latter operation phases where less accuracy is required.

Abstract translation: 算法模数转换器（ADC）包括采样保持电路和并行运行并共享单个运算放大器的ADC处理单元。 ADC处理单元包括具有开关电容拓扑和子ADC的MDAC。 ADC处理单元由比采样和保持时钟快N倍的内部时钟提供时钟。 每个周期进一步细分为两个阶段。 在一个阶段期间，电容器耦合到由MDAC提供的残留或采样电压，并且在另一阶段期间，电容器被耦合到由子ADC产生的开关控制信号确定的参考电压。 ADC处理单元在每个ADC时钟周期内产生一组数据位。 添加N组数据位以产生数字输出流。 内部时钟又具有可变周期，可以在需要更高精度的早期操作阶段分配更多时间，并且在需要较少精度的后期操作阶段中具有更少的时间。

公开(公告)号：US08654000B2

公开(公告)日：2014-02-18

申请号：US13603495

申请日：2012-09-05

Applicant: Mikko Waltari

Inventor： Mikko Waltari

IPC: H03M1/34

CPC classification number: H03M1/0626 ,  H03M1/0836 ,  H03M1/1215 ,  H03M1/1245

Abstract: Processing a signal by receiving an analog input signal located outside of a first Nyquist zone that is between 0 and fs/2; passing the analog input signal through an M-channel time-interleaved analog-to-digital converter (TI-ADC) to generate a TI-ADC output signal; and estimating and correcting a timing skew error in the TI-ADC output signal. Alternatively, an electronic circuit that includes an input for an analog input signal, an M-channel time-interleaved analog-to-digital converter (TI-ADC) and a timing skew error estimating and correcting circuitry. The analog input signal is located outside of a first Nyquist zone that is between 0 and fs/2. The TI-ADC receives the analog input signal and generates a TI-ADC output signal. The timing skew error estimating and correcting circuitry estimates and corrects a timing skew error in the TI-ADC output signal.

Abstract translation: 通过接收位于第一奈奎斯特区之外的位于0和fs / 2之间的模拟输入信号来处理信号; 通过M通道时间交织的模数转换器（TI-ADC）传递模拟输入信号，以产生TI-ADC输出信号; 并估计和校正TI-ADC输出信号中的定时偏移误差。 或者，包括用于模拟输入信号的输入端，M通道时间交替模数转换器（TI-ADC）和定时偏移误差估计和校正电路的电子电路。 模拟输入信号位于0和fs / 2之间的第一奈奎斯特区之外。 TI-ADC接收模拟输入信号并产生TI-ADC输出信号。 定时偏移误差估计和校正电路估计和校正TI-ADC输出信号中的定时偏移误差。

公开(公告)号：US07557746B1

公开(公告)日：2009-07-07

申请号：US12002153

申请日：2007-12-13

Applicant: Mikko Waltari

Inventor： Mikko Waltari

IPC: H03M1/34 ,  H03M1/50

CPC classification number: H03M1/206 ,  H03M1/365 ,  H03M1/50

Abstract: An analog-to-digital converter circuit comprises a first voltage comparator coupled to a first reference voltage and a signal voltage, the first voltage comparator having first negative and first positive outputs for outputting a comparison of the first reference voltage with the signal voltage; a second voltage comparator coupled to a second reference voltage and the signal voltage, the second reference voltage different than the first reference voltage, the second voltage comparator having second negative and second positive outputs for outputting a comparison of the second reference voltage with the signal voltage; and a first arrival time comparator coupled to the first positive output and the second negative output, the first arrival time comparator having a first arrival time comparator output for outputting a comparison of the first positive output with the second negative output.

Abstract translation: 模拟 - 数字转换器电路包括耦合到第一参考电压和信号电压的第一电压比较器，所述第一电压比较器具有第一负和第一正输出，用于输出第一参考电压与信号电压的比较; 第二电压比较器，其耦合到第二参考电压和所述信号电压，所述第二参考电压不同于所述第一参考电压，所述第二电压比较器具有第二负和第二正输出，用于输出所述第二参考电压与所述信号电压的比较 ; 以及耦合到第一正输出和第二负输出的第一到达时间比较器，第一到达时间比较器具有第一到达时间比较器输出，用于输出第一正输出与第二负输出的比较。

公开(公告)号：US07088275B2

公开(公告)日：2006-08-08

申请号：US10749570

申请日：2003-12-31

Applicant: Mikko Waltari

Inventor： Mikko Waltari

IPC: H03M1/12 ,  H03L7/06 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08

CPC classification number: H03M1/144

Abstract: An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing unit includes an MDAC with a switched capacitor topology and a sub-ADC. The ADC processing unit is clocked by an internal clock that is N times faster than the sample-and-hold clock. Each cycle is further sub-divided into two phases. During one phase the capacitors are coupled to a residue or sampled voltage provided by the MDAC, and during another phase the capacitor are coupled to a reference voltage determined by the switch control signals generated by the sub-ADC. A set of data bits is generated by the ADC processing unit during each ADC clock cycle. The N sets of data bits are added to generate the digital output stream. The internal clock, in turn, has a variable period allocating more time to the early operation phases where more accuracy is required and less time to the latter operation phases where less accuracy is required.

Abstract translation: 算法模数转换器（ADC）包括采样保持电路和并行运行并共享单个运算放大器的ADC处理单元。 ADC处理单元包括具有开关电容拓扑和子ADC的MDAC。 ADC处理单元由比采样和保持时钟快N倍的内部时钟提供时钟。 每个周期进一步细分为两个阶段。 在一个阶段期间，电容器耦合到由MDAC提供的残留或采样电压，并且在另一阶段期间，电容器被耦合到由子ADC产生的开关控制信号确定的参考电压。 ADC处理单元在每个ADC时钟周期内产生一组数据位。 添加N组数据位以产生数字输出流。 内部时钟又具有可变周期，可以在需要更高精度的早期操作阶段分配更多时间，并且在需要较少精度的后期操作阶段中具有更少的时间。

公开(公告)号：US07068202B2

公开(公告)日：2006-06-27

申请号：US10749571

申请日：2003-12-31

Applicant: Mikko Waltari

Inventor： Mikko Waltari

IPC: H03M1/12 ,  H03L7/06 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08

CPC classification number: H03M1/1245 ,  H03M1/466

Abstract: An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing unit includes an MDAC with a switched capacitor topology and a sub-ADC. The ADC processing unit is clocked by an internal clock that is N times faster than the sample-and-hold clock. Each cycle is further sub-divided into two phases. During one phase the capacitors are coupled to a residue or sampled voltage provided by the MDAC, and during another phase the capacitor are coupled to a reference voltage determined by the switch control signals generated by the sub-ADC. A set of data bits is generated by the ADC processing unit during each ADC clock cycle. The N sets of data bits are added to generate the digital output stream.

Abstract translation: 算法模数转换器（ADC）包括采样保持电路和并行运行并共享单个运算放大器的ADC处理单元。 ADC处理单元包括具有开关电容拓扑和子ADC的MDAC。 ADC处理单元由比采样和保持时钟快N倍的内部时钟提供时钟。 每个周期进一步细分为两个阶段。 在一个阶段期间，电容器耦合到由MDAC提供的残留或采样电压，并且在另一阶段期间，电容器被耦合到由子ADC产生的开关控制信号确定的参考电压。 ADC处理单元在每个ADC时钟周期内产生一组数据位。 添加N组数据位以产生数字输出流。